Frequency scaling will be software controlled: update PLL division ratio. PLL has inertia: e.g. 1 millisecond. Let's adjust the clock frequency (while keeping VCC constant for now). Does this help ?
Compare dynamic frequency adjustment with with dynamic clock gating:
|Clock Gating.||Frequency Adjustment.|
|Granularity:||register / FSM,||macroscopic.|
|Clock Tree:||mostly free runs,||slows down.|
|Can vary voltage:||no,||yes.|
To compute quickly and halt we need a higher frequency clock but consume the same number of active cycles.
So the work-rate product, af, unchanged, so no power difference ?
Actually un-stopped regions consume power proportional to f.
Zeno: Tortoise and Achilles ?
Tortoise is best: keep going steadily and end just in time. (He appeals even more when we vary the voltage.)
But, dynamic clock gating still very useful for: bursty, localised activity (which is the general case).