Our ESL flow is mainly based on C/C++. This language is used for behavioural models of the peripherals and for the embedded applications, operating system and device drivers.
For fabrication, the embedded software is compiled with the target compiler (e.g. gcc-arm) and RTL is converted to gates and polygons using Synopsys Design Compiler.
For ESL simulation, as much as possible, we take the original C/C++ and link it all together, whether it is hardware or software, and run it over the SystemC event-driven simulation (EDS) kernel.
Variations: sometimes we can import RTL components using a tool such as Verilator or VTOC. Sometimes we use an ISS to interpret the target processor machine code.