Structural Verilog

Level 1/3: Structural Verilog : Structural, Heirarchic, Netlist

        BEGIN subcircuit(clk, rst, q2);
           INPUT clk, rst;
           OUTPUT q2;
           Ff1   :  DFFR(clk, rst, a, q1, qb1);
           Ff2   :  DFFR(clk, rst, q1, q2, qb2);
           Ff3   :  DFFR(clk, rst, q2, q3, qb3);
           Nor   :  NOR2(a, q2, q3);
        END subcircuit;

Just a netlist.

There are no assignment statements that transfer data between registers in structural RTL (but it's still a form or RTL).