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Behavioural - `Non-Synthesisable' RTL continued

Schematic symbol and timing diagram for an edge-triggered RS flop.
   reg q;
   input set, clear;

   always @(posedge set) q = 1;
   always @(posedge clear) q = 0;

Here a variable is updated by more than one thread.

This component is commonly used in phase-locked loops. It can be modelled in Verilog, but is not supported for Verilog synthesis.

24: (C) 2008-11, DJ Greaves, University of Cambridge, Computer Laboratory.