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SRTL abstract syntax notes

The abstract syntax tree for synthesisable RTL supports a rich set of expression operators but just the assignment and branching commands (no loops). (Loops in synthesisable VHDL and Verilog are restricted to so-called structural generation statements that are fully unwound by the compiler front end and so have no data-dependent exit conditions).

22: (C) 2008-11, DJ Greaves, University of Cambridge, Computer Laboratory.