The design must be specified in terms of high-level requirements, such as function, throughput and power consumption.
Design capture: it is transferred from the marketing person's mind, back of envelope or or wordprocessor document into machine-readable form.
Architectural exploration will try different combinations of processors, memories and bus structures to find an implementation with good power and load balancing. A loosely-timed high-level model is sufficient to compute the performance of an architecture.
Detailed design will select IP (interlectual property) providers for all of the functional blocks, or else they will exist from previous in house designs and can be used without license fees, or else freshly written.
Logic synthesis will convert from behavioural RTL to structural RTL. Synthesis from formal high-level forms, including SysML statecharts, formal specifications of interfaces and behaviour is becoming possible.
Instruction set simulators for embedded processors are needed: purchased from third parties such as ARM and MIPS, or as a by-product of custom processor design.
The interface specifications (APIs) between components need to be stored: the IP-XACT format may be used.
High-level models that are never intended to be synthesisable and test bench components will also be coded, typically using SystemC.
After RTL synthesis using a target technology library we have a structural netlist that has no gate delays.
Place and route gives 2-D co-ordinates to each component and adds external I/O pads and puts wiring between the components.
RTL annotated with actual implementation gate delays gives a precise power and performance model. If performance is not up to par, design changes are needed.
A library of standard tests will be run every night and any changes that cause a previously-passing test to fail (regressions) will be automatically reported to the project manager.
Fabrication of masks is commonly the most expensive single step.