Please complete the following work over the Michaelmas Vacation (Dec/Jan 2010/11).
Please submit a printout of source code and console or waveform outputs for Exercise 1a and 1b. Deadline: First day Lent Full Term, Tue 18th Jan '11 (5 Marks).
One half should be done in RTL (Verilog or VHDL) and the other in SystemC.
This exercise is primarily designed to ensure that you are able to run the tools and have no obstacles in your working environment. Please contact D Greaves by email if you have any problem getting started.
Since this is just a preliminary exercise, full marks will be awarded for any reasonable attempt. Also, if any of your answer is not working to your satisfaction at the due deadline a resubmission without loss of credit can be organised.
To get started with the provided tools please look at this TOOLINFO LINK but also please feel free to use any other computers or tools that you have to hand (such as a free copy of Modelsim on your own laptop or a version of SystemC that you have compiled for yourself).
If you do Exercise 1a in Verilog (or VHDL) then please do Exercise 1b using SystemC and vice versa.
By 'component' we mean a SystemC 'SC_MODULE' or a Verilog 'module' or a VHDL 'entity'.
FA[i] := FA[i-1] + FA[i-2]and which also generates some sort of output so that we know it worked.
If you did Exercise 1a in Verilog (or VHDL) then please do this one using SystemC.
In this exercise you must decide how to model a 'packet' at some reasonable level of abstraction. A packet must contain an originating timestamp and perhaps some other information such as an incrementing counter value that resembles data.
You must also decide how to model an interface that can carry these packets. You can use shared variables to model wires (as is common in RTL) or you might use subroutine calling over the interface.