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Shortcomings of Verilog and VHDL (for HL-Synthesis).

Verilog and VHDL are languages focused more on simulation than logic synthesis. The rules for translation to hardware that define the `synthesisable subset' were standardised post the definitions of the language.

Circuit aspects that could readily be determined or decided by the compiler are frequently explicit or directly implicit in the source Verilog text. These aspects include the number of state variables, the size of registers and the width of busses. Having these details in the source text makes the design longer and less portable.

Perhaps the major shortcoming of Verilog (and VHDL) is that the language gives the designer no help with concurrency. That is, the designer must keep in her head any aspect of handshaking between logic circuts or shared reading of register resources. This is ironic since hardware systems have much greater parallelism than software systems.

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.