The advantages of using a general purpose language to describe both hardware and software are becoming apparent: designs can be ported easily and tested in software environments before implementation in hardware. There is also the potential benefit that software engineers can be used to generate ASICs: they are normally cheaper to employ than ASIC engineers! The practical benefit of such approaches is not fully proven, but there is great potential.
The software programming paradigm, where a serial thread of execution runs around between various modules is undoubtedly easier to design with than the forced parallelism of expressions found in RTL-style coding. Ideally, a new thread should only be introduced when there is a need for concurrent behaviour in the expression of the design. A product from »COMPILOGIC is typical of the new generation of such EDA tools. It claims the following:
We cannot compile general C/C++ programs to hardware.
Must be finite state:
A given function can generally be done in half as many clock cycles using twice as much silicon, although name aliases and control hazards (dependence on run time input data) can limit this. As well as the C/C++ input code we require additional directives over speed, area and perhaps power. The area directives may specify the number of RAMs or how to map arrays into shared DRAM.
Trading time for space is basically a matter of unwinding loops or introducing new loops.
Hazards can limit the amount of unrolling possible, including limited numbers of ports on RAMs and user-set budgets on the number of certain components instantiated, such as adders or multipliers. Products available : SystemCrafter, Catapult, SimVision, CoCentric, ... others.