Many RTL synthesisers support an implied program counter (state machine inference).
reg [2:0] yout; always begin @(posedge clk) yout = 1; @(posedge clk) yout = 4; @(posedge clk) yout = 3; end
In this example, not only is there a thread with current point of execution, but the implied `program counter' advances only partially around the body of the always loop on each clock edge. Clearly the compiler or synthesiser has to make up flip-flops not explicitly mentioned by the designer, to hold the current `program counter' value.
None of the event control statements is conditional in the example, but the method of compilation is readily extended to support this: it amounts to the program counter taking conditional branches. For example, the middle event control could be prefixed with 'if (din)'.
if (din) @(posedge clk) yout = 4;