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Automated Stimulus Generation

Simulations and test programs require stimulus. This is a sequence of input signals, including clock and reset, that exercise the design.

Given that formal specifications for many of the input port protocols might exist, one can consider automatic generation of the stimulus, from random sources, within the envelope defined by the formal specification. Several commercial products do this, including Verisity's Specman Elite, Synopsys Vera.

Here is an example of some code in Specman's own language, called `e', that defines a frame format used in networking. Testing will be inside envelope defined by keep statement.

struct frame {
  llc: LLCHeader;
  destAddr: uint (bits:48);
  srcAddr: uint (bits:48);
  size: int;  
  payload: list of byte;           
  keep payload.size() in [0..size];  };

Sequences of bits that conform to the frame structure are accepted at an input port of the design under test.

An heirarchy of specifications and constraints is supported. One can compose and extend one specification to reduce its possible behaviours:

  extend frame { keep size == 0;  };

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.