NEXT (ESL Evolution: Starting point for SoC Modelling: Pre-ESL.)
ESL: Electronic System Level Modelling
Aim 1: To Model whole SoC using real firmware and high-level behavioural models.
Aim 2: To allow seamless and successive replacement of model parts
with low-level models/implementations
when available and when interested in detail.
An ESL methodology provides:
- Tangible, lightweight rapidly-generated prototype of full SoC architecture.
- Rapid Architectural Evaluation: determine bus bandwidth and memory use for
a candidate architecture. Easy to adjust major design parameters.
- Algorithmic Accuracy: Get real output from an early system,
hosting the real application/firmware, possibly in real-time.
- Timing information:
Get timing numbers for performance (accurate or loose timing).
- Firmware development: Integrate high-level behavioural models of major components
with their device drivers.
Future topic: Embed assertions in the high-level models
and use these assertions through to tape out (ABD).
Increasingly the industry wants to synthesise behavioural models to become the
fabricated system, but today manual re-coding is the main way.