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ESL Evolution: Starting point for SoC Modelling: Pre-ESL.

ISS interprets binary machine code and an RTL simulator simulates hardware devices.

Pre-ESL, the main tool was the EDS simulator. An instruction set simulator (ISS or emulator) coded in RTL or actual RTL processor model can be used to interpret the firmware, but this runs very slowly, perhaps a million times slower than real time, meaning operating system boot would take a day of modelling.

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.