We are pleased to announce the 2017 NetFPGA Design Challenge!

NetFPGA platforms are used by the networked systems community for close to a decade. The platforms enable researchers and instructors to build high-speed, hardware-accelerated networking systems. The platforms can be used by researchers to prototype advanced services for next-generation networked systems. By using Field Programmable Gate Arrays (FPGAs), NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained.
The NetFPGA 2017 contest is a design challenge. The design teams are to produce a working implementation employing any HW and SW design methodology and targeting the NetFPGA SUME platform. The deadline for submissions is April 18th, 2017 (23:59:59 AOE). The winners will be announced at the NetFPGA Developers Summit (Thursday 20th - Friday, 21st April, 2017 Cambridge, UK).

Challenge: Lowest Latency Switch

Low latency devices are being increasingly used across a large number of applications. Low latency solutions are few, and are rarely open source. The goal of this challenge is to provide a usable, high performance, open source alternative to use by universities and organizations who need the flexibility of open source.
The systems will be evaluated using OSNT, an Open Source Network Tester. Test benches will be available online prior to workshop day, for users to experiment and independently evaluate their design.
The competition is open to students of all levels (undergraduate and postgraduate), as well as to non students. There is no need to own a NetFPGA SUME platform to take part in the competition although, clearly, development and testing will be made easier if you have access to this platform.

Team Prizes

First Place: £500

Best Students Project: £500

The design challenge prizes are generously supported by IMC

Registration

All teams must register. Each team is required to register only once.
Please register through this link.

Further Details

Eligibility and Registration

How do I register?
Please register using this link.
Who can participate in the challenge?
This contest is open to industry and academic institutions (faculty and/or students). A team may include both industry and academic members. Staff and faculty of the University of Cambridge, the judges, and their immediate family members cannot participate in this competition.
What should be the size of the team?
There is no limit on the size of a team. There is no limit on the number of teams per institution.
We have a mixed team of… are we eligible for the students prize?
To be eligible for the students prize, only students may take part in your team. The students may be both undergraduate and postgraduate. If your academic supervisor takes an active part in your team (e.g. by contributing code) you will not be eligible for the students prize.
What happens is a students team wins the first place?
If a students team wins the first place, they would receive both the first place prize and the best students project prize.
Are team mergers allowed? Can teams have members from different institutions?
Yes. Team mergers are allowed as well as mixed teams from different institutions.
How many submissions are allowed per day?
We currently allow one submission per day.
Final submission
The date for the final submission is **EXTENDED** April-18th, 2017 (23:59:59 AOE). Only the final submission is counted toward the prize, regardless the results of previous submissions. Final submission link will be sent to registered participants.
Presentation
A selected set of projects, including the winning projects, will be invited to present their work at the NetFPGA developers workshop.
All challenge participants are entitled to a reduced registration fee at the NetFPGA developers workshop.

Platform and Design License

I don’t have a NetFPGA SUME board
Owning a NetFPGA SUME board is not a must. The projects are evaluated on our platform. However, we do not provide any debug access, thus having a platform is recommended. (You can also make a donation request to Xilinx for a board to use for your project.)
Can I use a different platform?
No. Only the NetFPGA SUME platform can be used for this challenge.
I don’t have a license
You can request Xilinx licenses from the Xilinx University Program. All cores used by the project need to be open source cores or cores provided free of charge by Xilinx.

The mailing list for questions, comments and interaction is cl-netfpga-dev2017@lists.cam.ac.uk. This mailing list is shared between all contestants.

Getting Started and Support

Where can I learn about the NetFPGA platform?
www.netfpga.org
Where can I learn about the NetFPGA SUME platform?
Either on www.netfpga.org or refer to the paper: Noa Zilberman, Yury Audzevich, Adam Covington, Andrew W. Moore. "NetFPGA SUME: Toward 100Gbps as Research Commodity", IEEE Micro, vol.34, no.5, pp.32,41, September-October 2014.
Where can I learn how to use NetFPGA-SUME?
The first place to start in the wiki. You can also refer to our previous events, and in particular to the half-day tutorial at FPL’15 and the week long course at the Technion.
Where can I learn about OSNT?
http://osnt.org/ or refer to the paper: Gianni Antichi, Muhammad Shahbaz, Yilong Geng, Noa Zilberman, Adam Covington, Marc Bruyere, Nick McKeown, Nick Feamster, Bob Felderman, Michaela Blott, Andrew W. Moore, Philippe Owezarski. "OSNT: Open Source Network Tester", IEEE Network, IEEE Network, vol.28, no.5, pp.6,12, September-October 2014
Can I use the NetFPGA reference projects as the basis for my design?
Yes, you can use any material on the NetFPGA repository as the basis for your design.
What if I have any questions?
The mailing list for questions, comments and interaction is cl-netfpga-dev2017@lists.cam.ac.uk. This mailing list is shared between all contestants.

Design

What is the design expected to do?
The design in expected to provide a low latency, layer two, learning switch. The design is expected to provide full line rate transactions from any port to any port, supporting 4 x 10GE. The bandwidth performance is expected to be at least the same as the NetFPGA SUME Reference Switch design. Supported packet sizes should range from 64B to 1518B (including Ethernet header, but excluding preamble and IPG). More clarifications will be posted here if need be.
What should be the design stages?
We recommend the following design stages:
- Design of a pipeline supporting low latency for a single port, tested with a single packet or low rate traffic.
- Design of a pipeline supporting low latency for a single port, tested at full data rate.
- Design of a pipeline supporting low latency for four ports.
The evaluation tests are adapted to this concept, however it is not mandatory.
What should be the properties of the switch?
- The switch should be a learning switch - i.e. no static entries.
- All packet sizes (64B-1518B) should be supported, with similar performance.
- Full line rate should be supported.
Is this a Layer 2 / Layer 3 switch?
This is a layer 2 switch, where switching is done based on the Ethernet header.
How many forwarding rules the switch needs to support?
The switch should support at least 16 rules. Refer to the Reference Switch’s Output Port Lookup as an example.
Which modules should be included in the design?
You can include any modules that you like in the design. A DMA engine (for traffic to the host) is not a requirement.
Can I used non-open source cores?
Only open source cores are allowed. An exception is cores provided by Xilinx Vivado IP Library free of charge. These must be cores provided free of charge for every user, and not a license for a core obtained free of charge for a specific user. A second exception is the 10G Ethernet Port IP used by the NetFPGA SUME reference designs. Note that an open 10G MAC core is now available under NetFPGA SUME contrib cores, release 1.4.0.
Which design languages are allowed?
You can use verilog and vhdl. You can also use other programming languages, as long as their use doesn’t enforce any limitations on making the project available as open source. Contact the NetFPGA team if in doubt.
Can I use code from projects I released or published in the past?
Yes, as long as the project will be made available under an open source license as explained below.

Evaluation

How is a design evaluated?
- Submit bitfile.
- The test platform is programmed with the bitfile.
- Three tests are conducted:
- The results are posted at this link
The evaluation plan is subject to change. Please follow this page for updates.
How to submit a bitfile?
Each registered team is sent a link through which they can upload their bitfile. The bitfile must be called switch.bit
How often are designs evaluated?
Designs are evaluated once a week (subject to change).
What tools are used for the evaluation?
OSNT is used for the evaluation.
How is latency measured?
Latency is measured from a start of packet (Tx) to a start of packet (Rx).
Which packet sizea are used for evaluation?
64B to 1518B.
Where can I find the test suite?
The test suite is available as part of the OSNT SUME repository under contrib/challenge2017. You may need to register to OSNT to gain access to the repository.
How do I report a bug or a limitation of the evaluation environment?
Please send an email to the mailing list at cl-netfpga-dev2017@lists.cam.ac.uk.
Can I contribute additional evaluation tests?
Yes! We encourage people to contribute tests. However, ranking will be done based on the basic tests, subject to erratas.

Open Source

To be eligible, all designs must be contributed to the NetFPGA repository. Instructions on how to contribute and the requirements are available on the NetFPGA-SUME wiki. All NetFPGA contributions are freely distributed under an Apache-style license. License details can be found on the wiki. If you have questions or concerns about licensing, please contact the NetFPGA team.

Where can I find details about the license?
License details can be found at https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/License.
Who owns the copyrights for my work?
You do! Copyrights and redistribution license are two different things.
How do I contribute code?
Contributing code
Can I used code developed under a different license?
If your code was already published under a different license, please contact the NetFPGA team. Otherwise, we expect all code to be published under the NetFPGA C.I.C license.
Can I submit a conference / journal paper based on my design?
Yes! We encourage participants to publish their work. We request all papers to cite this challenge. Citation details are TBD.

Ranking

Where can I find the teams ranking?
At this link
Which test determines the winner of the challenge?
The full rate, 4 port experiment.
What happens if there is a tie in latency results?
The tie breaker will be the latency for a transmission from one of the ports to the host (i.e. using a DMA).
The results on my machine are different than yours.
The results on the Cambridge machines are the official ones. Send an email to the mailing list if you believe there is a bug or a problem with the evaluation environment.
Why do you publish the results?
It allows people to compare and improve their results. No design information will be posted online, only latency results.
How often do you publish results?
Once a week (subject to change).
Why was my design disqualified?
Reasons for disqualification are multiple, primarily not submitting your project as an open source or using non open-source cores.
When will you announce the winners?
The winners will be announced on the NetFPGA developers workshop, April 21th, 2017.

Break the system

During the developer's’ workshop we will invite attendees to try and break (or demonstrate breaking) the winning designs. No NetFPGA platforms will be harmed during this session. Unless an experiment will demonstrate that a design violated the evaluation tests or the intent of the challenge, this will not affect the contest results.