OR1K Blocking TLM Reference Design.
The main hardware simulation platform we plan to use in this course - but not showing caches etc..
Can load and run the pre-compiled 'hello' and 'mixbug' examples.
It's actually a multi-core processor but defaults to just one OR1200.
DJ Greaves will install a new version of the complete simulation platform on the fileserver as soon as we have finished looking at the toy version.
| 1: (C) 2012-18, DJ Greaves, University of Cambridge, Computer Laboratory. |