Shortcomings of Verilog and VHDL as Algorithmic Expression Languages

There is no expression of which state variables are live and which are idle.

Too much is explicit in the source Verilog text:

• number of state variables,
• size of registers, width of busses

Although highly-concurrent, no indication of what aspects of the concurrency are important.

Cannot use software design paradigms, such as sending a thread between components with implied flow control.