Classical High-Level Synthesis Continued

• Works well when there is little or no cycle time variation. Not so good with DRAM+cache or floating point.
• Creates a precise schedule of addresses on register file and RAM ports and ALU function codes.
• Typically unwinds inner loops by some factor.
• Can cope with data-dependent control flow. But relies on predicate hoisting when datapath is heavily pipelined (rather than speculation).
• Data-dependent control flow and RAM bandwidth ultimately limit parallelism.

Profile-directed guidance or explicit datapath description hints, such as unroll progmas, or explicit datapath description hints, such as unroll progmas, are needed for a sensible datapath structure since sequencer states are not equiprobable and we do not want to deploy resource on seldom-used data paths.

For example, best mapping of the record fields x and y to RAMs is different in the two foreach loops:

    class IntPair
    {   
	public bool c;     public int x, y;
    }

    IntPair [] ipairs = new IntPair [1024];

    void customer(bool qcond)
    {
        int sum1 = 0, sum2 = 0;
        if (qcond) then foreach (IntPair pp in ipairs)
         {   
             sum1 += pp.x + pp.y;
         }
        else foreach (IntPair pp in ipairs)
         {   
             sum2 += pp.c ? pp.y: pp.x;
         }
      ...
    }

The fields x and y could be kept in separate RAMs or a common one. If qcond rarely holds then a common RAM will serve since there is little contention. Whereas if qcond holds most of the time then keeping x and y in separate RAMs will boost performance. When dual-port RAMs are available, serving x and y from separate ports of a common RAM could also be used when qcond is frequent.