The output from HLS is RTL and instances of a structural components. The RTL will then be converted to logic gates by a Logic Synthesiser. Some of the structural components will also be synthesised to logic gates by the RTL compiler but others, especially RAMs and larger ALUs, will have custom implementations in the target technology.
Apart from the specification of the function itself, such as multiply, a block that performs a function in some number of clock cycles can be characterised using the following metrics:
A unit whose initiation interval is one is said to be Fully Pipelined.
In today's ASIC and FPGA technology, combinational add and subtract of up to 32-bit words is typical. But RAM read, multiply and divide are usually allocated at least one pipeline cycle, with larger multiplies and all divides being two or more.
For 64-bit word widths, floating point or RAMs larger than L1 size (e.g. 32 KByte), two or more cycle latency is common, but with an initiation interval of one (ii=1).
|20: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.|