Functional Unit (FU) Block Properties

Apart from the specification of the function itself, such as multiply, a block that performs a function in some number of clock cycles can be characterised using the following metrics:

• int Precision
• bool Referentially-Transparent (Stateless): always same result for same arguments.
• bool EIS (An end in itself): Has unseen side effects such as turning on an LED
• bool FL or VL: Fixed or Variable latency
• int Block latency: cycles to wait from arguments in to result out (or average if VL)
• int Initiation Interval: minimum number of cycles between starts (arguments in time) (or average if VL)
• real Energy: Joules per operation - normally a few nanojoules for a ...
• real Gate count or area: Area is typically given in square microns or, for FPGA, number of LUTs.

A unit whose initiation interval is one is said to be `fully pipelined'.

In today's ASIC and FPGA technology, combinational add and subtract of up to 32-bit words is typical. But RAM read, multiply and divide are usually allocated at least one pipeline cycle, with larger multiplies and all divides being two or more.

For 64-bit word widths, floating point or RAMs larger than L1 size (e.g. 32 KByte), two or more cycle latency is common, but with an initiation interval of one (ii=1).