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ABD - Boolean Equivalence Checker

Often we have two implementations of a combinational circuit to check for equivalence. For example, they might be:

  1. RTL version: pre-synthesis,
  2. Gate-level version: post-synthesis or post-layout.

Error sources: manual implementation of one of them, manual edits to synthesiser outputs and EDA tool faults.

Boolean equivalence: do the two functions produce the same output?

Method: Create a MITRE of the two designs using a disjunction of XOR gate outputs.

Then: feed negation of mitre to a SAT solver.

Result: if there are no solutions, designs are equivalent.

26: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.