ECAD and Architecture Practical Classes
Principal lecturer: Prof Simon Moore
Taken by: Part IB CST
Term: Michaelmas
Format: In-person lectures
Prerequisites: Digital Electronics
Moodle, timetable
Aims
The aims of this course are to enable students to apply the concepts learned in the Introduction to Computer Architecture course. In addition, there is further online training to learn the SystemVerilog hardware description language. SystemVerilog is then used for the online ticks that culminate in using a SystemVerilog RISC-V processor and a tick that involves writing RISC-V assembler.
Practical Classes
- Online learning of SystemVerilog.
- Design, simulation and test of SystemVerilog design hardwares.
- Simulating a RISC-V processor designed in SystemVerilog. Writing assembler for this processor and simulating it in a “bare metal” (i.e. without an Operating System) environment.
Objectives
- Gain experience in electronic computer aided design (ECAD) through learning a design-flow for SystemVerilog, a hardware description language widely used in industry.
- Learn how to debug hardware and software systems in simulation.
Recommended reading
Recommended reading
* Harris, S.L. and Harris, D.M. (2021).Digital Design and Computer Architecture, RISC-V Edition, Morgan Kaufmann. Note that the authors' earlier work is still of relevance - Digital design and computer architecture: from gates to processors - first edition in 2007 and second edition in 2012.