Course pages 2017–18
Computer Design
Principal lecturers: Prof Simon Moore, Dr Timothy Jones
Taken by: Part IB CST 50%, Part IB CST 75%
Past exam questions
No. of lectures: 18 (plus 4 via a web-based tutor)
Suggested hours of supervisions: 5
Prerequisite course: Digital Electronics
Companion course: Electronic Computer Aided Design (ECAD)
This course is a prerequisite for the Part II courses Comparative Architectures and System-on-Chip Design.
Aims
The aims of this course are to introduce a hardware description language (SystemVerilog) and computer architecture concepts in order to design computer systems. The parallel ECAD+Arch practical classes will allow students to apply the concepts taught in lectures.
The course starts with a web-based SystemVerilog tutor which is a prerequisite for the ECAD+Arch practical classes. There are then eighteen lectures in three six-lecture parts. Part 1 goes from gates to a simple processor. Part 2 looks at instruction set and computer architecture. Part 3 analyses the architecture of modern systems-on-chip.
Lectures
Part 0 - SystemVerilog Web tutor
- This web tutor is a prerequisite to starting the ECAD+Arch laboratory sessions [equivalent to approximately 4 lectures]
Part 1 - Gates to processors [lecturer: Simon Moore]
- Introduction and motivation. [1 lecture]
Current technology, technology trends, ECAD trends, challenges.
- Logic modelling, simulation and synthesis. [1 lecture]
Logic value and delay modelling. Discrete event and device
simulation. Automatic logic minimization.
- SystemVerilog FPGA design. [1 lecture]
Practicalities of mapping SystemVerilog descriptions of hardware
(including a processor) onto an FPGA
board. Tips and pitfalls when generating larger modular designs.
- Chip, board and system testing. [1 lecture]
Production testing, fault models, testability, fault coverage,
scan path testing, simulation models.
- Building a simple computer. [2 lectures]
Part 2 - Instruction sets and introduction to computer architecture [lecturer: Simon Moore]
- Historical perspective on computer architecture. [1 lecture]
EDSAC versus Manchester Mark I.
- RISC machines. [1 lecture]
Introduction to ARM and MIPS RISC processor designs.
- CISC and virtual machines [1 lecture]
The Intel x86 instruction set and the Java Virtual Machine (JVM).
- Memory hierarchy. [1 lecture]
Caching, etc.
- Hardware support for operating systems. [1 lecture]
Memory protection, exceptions, interrupts, etc.
- Pipelining and data paths. [1 lecture]
Part 3 - Systems-on-chip [lecturer: Timothy Jones]
- Overview of Systems-on-Chip (SoCs) and DRAM. [1 lecture]
High-level SoCs, DRAM storage and accessing.
- Multicore Processors. [2 lectures]
Communication, cache coherence, barriers and synchronisation primitives.
- Graphics processing units (GPUs) [2 lectures]
Basic GPU architecture and programming.
- Future Directions [1 lecture]
Where is computer architecture heading?
Objectives
At the end of the course students should
- be able to read assembler given a guide to the instruction set
and be able to write short pieces of assembler if given an
instruction set or asked to invent an instruction set;
- understand the differences between RISC and CISC assembler;
- understand what facilities a processor provides to support
operating systems, from memory management to software interrupts;
- understand memory hierarchy including different cache
structures and coherency needed for multicore systems;
- understand how to implement a processor in SystemVerilog;
- appreciate the use of pipelining in processor design;
- have an appreciation of control structures used in processor design;
- have an appreciation of system-on-chips and their components;
- understand how DRAM stores data;
- understand how multicore processors communicate;
- understand how GPUs work and have an appreciation of how to program them.
Recommended reading
* Patterson, D.A. & Hennessy, J.L. (2017). Computer organization and design: The hardware/software interface RISC-V edition. Morgan Kaufmann. ISBN 978-0-12-812275-4.
Recommended further reading:
Harris, D.M. & Harris, S.L. (2012). Digital design and computer architecture. Morgan Kaufmann. ISBN 978-0-12-394424-5.
Hennessy, J. & Patterson, D. (2006). Computer architecture: a quantitative approach. Elsevier (4th ed.). ISBN 978-0-12-370490-0. (Older versions of the book are also still generally relevant.)
Pointers to sources of more specialist information are included in the lecture notes and on the associated course web page.