Reversible Discrete Event Simulation
Title : Reversible Discrete Event Simulation
Originator : Simon Moore
Special Resources : none
Background
Discrete event simulation is a well known technique for simulating concurrent
systems (e.g. circuits). One approach is to model the behavioural
characteristics of each component at an abstract level and then interconnect
using (virtual) timed messages.
For teaching purposes it would be nice to be able to demonstrate a system
(e.g. an ARM processor pipeline) running both forward and in reverse. The
behavioural models would only need to know about progressing messages forward
- reversing would be performed by storing state changes so that the discrete
event simulation kernel can force a backtrack.
Related Past Projects
This project would build upon the ideas from previous tripos projects:
- "Time Warp" by Jagdip Grewal (1993) and
- "An Animated ARM" by Robin Hughes (1995)
Some Extensions
- an interesting application
- graphical representation of a running simulation
- parallel processing (e.g. using time warp ideas)
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