Test Z6.2+sync+addr+addr

Run Z6.2+sync+addr+addr in model, using ppcmem

PPC Z6.2+sync+addr+addr
"SyncdWW Rfe DpAddrdW Rfe DpAddrdW Wse"
Cycle=Rfe DpAddrdW Rfe DpAddrdW Wse SyncdWW
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z;
2:r2=z; 2:r5=x;
}
 P0           | P1            | P2            ;
 li r1,2      | lwz r1,0(r2)  | lwz r1,0(r2)  ;
 stw r1,0(r2) | xor r3,r1,r1  | xor r3,r1,r1  ;
 sync         | li r4,1       | li r4,1       ;
 li r3,1      | stwx r4,r3,r5 | stwx r4,r3,r5 ;
 stw r3,0(r4) |               |               ;
exists
(x=2 /\ 1:r1=1 /\ 2:r1=1)