Test Z6.2+lwsync+addr+sync

Run Z6.2+lwsync+addr+sync in model, using ppcmem

PPC Z6.2+lwsync+addr+sync
"LwSyncdWW Rfe DpAddrdW Rfe SyncdRW Wse"
Cycle=Rfe SyncdRW Wse LwSyncdWW Rfe DpAddrdW
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z;
2:r2=z; 2:r4=x;
}
 P0           | P1            | P2           ;
 li r1,2      | lwz r1,0(r2)  | lwz r1,0(r2) ;
 stw r1,0(r2) | xor r3,r1,r1  | sync         ;
 lwsync       | li r4,1       | li r3,1      ;
 li r3,1      | stwx r4,r3,r5 | stw r3,0(r4) ;
 stw r3,0(r4) |               |              ;
exists
(x=2 /\ 1:r1=1 /\ 2:r1=1)