Test Z6.1+lwsync+po+addr

Run Z6.1+lwsync+po+addr in model, using ppcmem

PPC Z6.1+lwsync+po+addr
"LwSyncdWW Wse PodWW Rfe DpAddrdW Wse"
Cycle=Rfe DpAddrdW Wse LwSyncdWW Wse PodWW
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z;
2:r2=z; 2:r5=x;
}
 P0           | P1           | P2            ;
 li r1,2      | li r1,2      | lwz r1,0(r2)  ;
 stw r1,0(r2) | stw r1,0(r2) | xor r3,r1,r1  ;
 lwsync       | li r3,1      | li r4,1       ;
 li r3,1      | stw r3,0(r4) | stwx r4,r3,r5 ;
 stw r3,0(r4) |              |               ;
exists
(x=2 /\ y=2 /\ 2:r1=1)