Test Z6.0+sync+addr+po

Run Z6.0+sync+addr+po in model, using ppcmem

PPC Z6.0+sync+addr+po
"SyncdWW Rfe DpAddrdW Wse PodWR Fre"
Cycle=Rfe DpAddrdW Wse PodWR Fre SyncdWW
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z;
2:r2=z; 2:r4=x;
}
 P0           | P1            | P2           ;
 li r1,1      | lwz r1,0(r2)  | li r1,2      ;
 stw r1,0(r2) | xor r3,r1,r1  | stw r1,0(r2) ;
 sync         | li r4,1       | lwz r3,0(r4) ;
 li r3,1      | stwx r4,r3,r5 |              ;
 stw r3,0(r4) |               |              ;
exists
(z=2 /\ 1:r1=1 /\ 2:r3=0)