Test 3.LB+sync+addr+addr

Run 3.LB+sync+addr+addr in model, using ppcmem

PPC 3.LB+sync+addr+addr
"SyncdRW Rfe DpAddrdW Rfe DpAddrdW Rfe"
Cycle=Rfe SyncdRW Rfe DpAddrdW Rfe DpAddrdW
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z;
2:r2=z; 2:r5=x;
}
 P0           | P1            | P2            ;
 lwz r1,0(r2) | lwz r1,0(r2)  | lwz r1,0(r2)  ;
 sync         | xor r3,r1,r1  | xor r3,r1,r1  ;
 li r3,1      | li r4,1       | li r4,1       ;
 stw r3,0(r4) | stwx r4,r3,r5 | stwx r4,r3,r5 ;
exists
(0:r1=1 /\ 1:r1=1 /\ 2:r1=1)