Test 3.LB+addr+lwsync+po

Run 3.LB+addr+lwsync+po in model, using ppcmem

PPC 3.LB+addr+lwsync+po
"DpAddrdW Rfe LwSyncdRW Rfe PodRW Rfe"
Cycle=Rfe PodRW Rfe DpAddrdW Rfe LwSyncdRW
{
0:r2=x; 0:r5=y;
1:r2=y; 1:r4=z;
2:r2=z; 2:r4=x;
}
 P0            | P1           | P2           ;
 lwz r1,0(r2)  | lwz r1,0(r2) | lwz r1,0(r2) ;
 xor r3,r1,r1  | lwsync       | li r3,1      ;
 li r4,1       | li r3,1      | stw r3,0(r4) ;
 stwx r4,r3,r5 | stw r3,0(r4) |              ;
exists
(0:r1=1 /\ 1:r1=1 /\ 2:r1=1)