Test S+isync+addr

Run S+isync+addr in model, using ppcmem

PPC S+isync+addr
"ISyncdWW Rfe DpAddrdW Wse"
Cycle=Rfe DpAddrdW Wse ISyncdWW
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=x;
}
 P0           | P1            ;
 li r1,2      | lwz r1,0(r2)  ;
 stw r1,0(r2) | xor r3,r1,r1  ;
 isync        | li r4,1       ;
 li r3,1      | stwx r4,r3,r5 ;
 stw r3,0(r4) |               ;
exists
(x=2 /\ 1:r1=1)