Test S+po+ctrlisync

Run S+po+ctrlisync in model, using ppcmem

PPC S+po+ctrlisync
"PodWW Rfe DpCtrlIsyncdW Wse"
Cycle=Rfe DpCtrlIsyncdW Wse PodWW
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=x;
}
 P0           | P1           ;
 li r1,2      | lwz r1,0(r2) ;
 stw r1,0(r2) | cmpw r1,r1   ;
 li r3,1      | beq  LC00    ;
 stw r3,0(r4) | LC00:        ;
              | isync        ;
              | li r3,1      ;
              | stw r3,0(r4) ;
exists
(x=2 /\ 1:r1=1)