Test RWC+addr+isync

Run RWC+addr+isync in model, using ppcmem

PPC RWC+addr+isync
"Rfe DpAddrdR Fre ISyncdWR Fre"
Cycle=Rfe DpAddrdR Fre ISyncdWR Fre
{
0:r2=x;
1:r2=x; 1:r5=y;
2:r2=y; 2:r4=x;
}
 P0           | P1            | P2           ;
 li r1,1      | lwz r1,0(r2)  | li r1,1      ;
 stw r1,0(r2) | xor r3,r1,r1  | stw r1,0(r2) ;
              | lwzx r4,r3,r5 | isync        ;
              |               | lwz r3,0(r4) ;
exists
(1:r1=1 /\ 1:r4=0 /\ 2:r3=0)