Test WRC+isync+ctrl

Run WRC+isync+ctrl in model, using ppcmem

PPC WRC+isync+ctrl
"Rfe ISyncdRW Rfe DpCtrldR Fre"
Cycle=Rfe ISyncdRW Rfe DpCtrldR Fre
{
0:r2=x;
1:r2=x; 1:r4=y;
2:r2=y; 2:r4=x;
}
 P0           | P1           | P2           ;
 li r1,1      | lwz r1,0(r2) | lwz r1,0(r2) ;
 stw r1,0(r2) | isync        | cmpw r1,r1   ;
              | li r3,1      | beq  LC00    ;
              | stw r3,0(r4) | LC00:        ;
              |              | lwz r3,0(r4) ;
exists
(1:r1=1 /\ 2:r1=1 /\ 2:r3=0)