# Errata for Precise exceptions in relaxed architectures, ISCA 2025

Page 6 Figure 7 (right), MP+dmb.sy+ctrlelr. In the listing, in T1 handler, instruction 5 should read `MSR ELR_EL1,X5`.  This was just a transcription error in the paper; the isla and system-litmus-harness versions have the correct code.