2011-06-27 Jaroslav Sevcik - started the document, compiling various sources 2011-06-28 Jaroslav Sevcik, Peter Sewell - minor tweaks in wording, fixing typos - added Power, ARM spinlock implementations - fixed ARM cmpxchg sequence (taken from Linux) 2011-06-29 Jaroslav Sevcik Incorporated various email suggestions: - added a discussion of other approaches to the mappings, esp. the one that describes compilation of program-order-adjacent pairs of accesses (suggested by Doug Lea) - parenthesised LOCK in x86-store-seq-cst (suggested by Hans Boehm) - updated the link to Paul McKenney's PowerPC mappings (suggested by Alexander Terekhov) - updated Itanium mappings with the CAS sequences (Hans) - removed mf from Itanium's seq-cst load (Hans) - fixed load-consume (to be ld.acq) on Itanium (Hans) - added x64 to x86 mappings (Doug) - added the DMB variant to ARM load-acquire, seq-cst (Alasdair Grant) - added dependency preservation note + barrier approach to consume for Power and ARM (suggested by Hans) - added a note on 64-bit relaxed atomic access on ARM (Alasdair) 2011-06-30 Jaroslav Sevcik - fixed Itanium relaxed-store mapping (st -> st.rel) (suggested by Alexander, example due to Hans) An example motivating the fix: Thread 1: r3 = y.load(mo_acquire); // sees 1 r1 = x.load(mo_relaxed) // sees 0 Thread 2: x.store(1, mo_relaxed) Thread 3: r2 = x.load(mo_relaxed); // sees 1 y.store(1, mo_release) In C++, the outcome r2=r3=1, r1=0 is not allowed. On Itanium with relaxed stores compiled to st, this outcome would be possible because the store to x might become visible to thread 3 early, but to thread 1 late. 2011-07-01 Jaroslav Sevcik - changed acq-, rel-, acq-rel-fence to no-op on Itanium (suggested by Alexander and Hans) This is fine because all atomic accesses are releases or acquires anyway. 2011-07-20 Jaroslav Sevcik - added a sentence on non-temporal stores for x86 (suggested by Hans) 2011-12-22 Peter Sewell - added discussion of the two ARM SC atomic mappings in play, replacing the main suggestion by the mapping that puts DMB before and after SC stores 2014-06-12 Peter Sewell - added proposed mappings for ARMv8 from Richard 2015-04-11 Peter Sewell - fixed ARMv7 CMPXCHG issue identified by Robin 2016-07-08 Peter Sewell, ARM fixes from Will Deacon - annotated ARM DMB barrier with ISH (inner shareability domain). The shareability domain is syntactically required for AArch64 - added note about LPAE and LDRD/STRD - added note that ARMv8 AArch32 SC mapping doesn't interwork with the ARMv7 mapping. ARMv8 fixes from Szabolcs Nagy: - cbnz rres, _loop; instead of cbz rres, _loop; - b.ne instead of bne x86 notes from JF Bastian: - a LOCK'd identity operation to the top of stack 2016-10-10 Peter Sewell - add note about ARMv7 acquire based on Will Deacon remarks