Test WRW+2W+addr+dsb

Run WRW+2W+addr+dsb in model, using armmem

ARM WRW+2W+addr+dsb
"Rfe DpAddrdW Wse DSBdWW Wse"
Cycle=Rfe DpAddrdW Wse DSBdWW Wse
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1               | P2            ;
 MOV R0, #2    | LDR R0, [%x1]    | MOV R0, #2    ;
 STR R0, [%x0] | EOR R1,R0,R0     | STR R0, [%y2] ;
               | MOV R2, #1       | DSB           ;
               | STR R2, [R1,%y1] | MOV R1, #1    ;
               |                  | STR R1, [%x2] ;
exists
(x=2 /\ y=2 /\ 1:R0=2)