Test S+isb+ctrl

Run S+isb+ctrl in model, using armmem

ARM S+isb+ctrl
"ISBdWW Rfe DpCtrldW Wse"
Cycle=Rfe DpCtrldW Wse ISBdWW
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 MOV R0, #2    | LDR R0, [%y1] ;
 STR R0, [%x0] | CMP R0, R0    ;
 ISB           | BNE LC00      ;
 MOV R1, #1    | LC00:         ;
 STR R1, [%y0] | MOV R1, #1    ;
               | STR R1, [%x1] ;
exists
(x=2 /\ 1:R0=1)