Test S+dsb+addr

Run S+dsb+addr in model, using armmem

ARM S+dsb+addr
"DSBdWW Rfe DpAddrdW Wse"
Cycle=Rfe DpAddrdW Wse DSBdWW
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1               ;
 MOV R0, #2    | LDR R0, [%y1]    ;
 STR R0, [%x0] | EOR R1,R0,R0     ;
 DSB           | MOV R2, #1       ;
 MOV R1, #1    | STR R2, [R1,%x1] ;
 STR R1, [%y0] |                  ;
exists
(x=2 /\ 1:R0=1)