Test RWC+addr+dsb

Run RWC+addr+dsb in model, using armmem

ARM RWC+addr+dsb
"Rfe DpAddrdR Fre DSBdWR Fre"
Cycle=Rfe DpAddrdR Fre DSBdWR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1               | P2            ;
 MOV R0, #1    | LDR R0, [%x1]    | MOV R0, #1    ;
 STR R0, [%x0] | EOR R1,R0,R0     | STR R0, [%y2] ;
               | LDR R2, [R1,%y1] | DSB           ;
               |                  | LDR R1, [%x2] ;
exists
(1:R0=1 /\ 1:R2=0 /\ 2:R1=0)