Test RWC+ctrl+dmb

Run RWC+ctrl+dmb in model, using armmem

ARM RWC+ctrl+dmb
"Rfe DpCtrldR Fre DMBdWR Fre"
Cycle=Rfe DpCtrldR Fre DMBdWR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1            | P2            ;
 MOV R0, #1    | LDR R0, [%x1] | MOV R0, #1    ;
 STR R0, [%x0] | CMP R0, R0    | STR R0, [%y2] ;
               | BNE LC00      | DMB           ;
               | LC00:         | LDR R1, [%x2] ;
               | LDR R1, [%y1] |               ;
exists
(1:R0=1 /\ 1:R1=0 /\ 2:R1=0)