Test LB+dsb+ctrlisb

Run LB+dsb+ctrlisb in model, using armmem

ARM LB+dsb+ctrlisb
"DSBdRW Rfe DpCtrlIsbdW Rfe"
Cycle=Rfe DSBdRW Rfe DpCtrlIsbdW
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 LDR R0, [%x0] | LDR R0, [%y1] ;
 DSB           | CMP R0, R0    ;
 MOV R1, #1    | BNE LC00      ;
 STR R1, [%y0] | LC00:         ;
               | ISB           ;
               | MOV R1, #1    ;
               | STR R1, [%x1] ;
exists
(0:R0=1 /\ 1:R0=1)