Test LB+ctrlisb+ctrl

Run LB+ctrlisb+ctrl in model, using armmem

ARM LB+ctrlisb+ctrl
"DpCtrlIsbdW Rfe DpCtrldW Rfe"
Cycle=Rfe DpCtrldW Rfe DpCtrlIsbdW
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 LDR R0, [%x0] | LDR R0, [%y1] ;
 CMP R0, R0    | CMP R0, R0    ;
 BNE LC00      | BNE LC01      ;
 LC00:         | LC01:         ;
 ISB           | MOV R1, #1    ;
 MOV R1, #1    | STR R1, [%x1] ;
 STR R1, [%y0] |               ;
exists
(0:R0=1 /\ 1:R0=1)