Key: ELF symbol (primary) ELF symbol source (with column ║) frame instruction +variable (range start) -variable (range end) inlining control-flow forwards branch ──> backwards branch ══>Compilation unit 0000c258 0000f090 arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
instructions
header
.debug_abbrev die abbreviation table
.debug_info die tree
.debug_line line number info
.debug_line evaluated line info
simple die tree
simple die tree globals
simple die tree locals
inlined subroutine info
inlined subroutine info by range
**0000c258 <__vgic_v3_save_state>:
0000c258 <$x>:
+ __vgic_v3_save_state params:
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc258 0xc3b0 (DW_OP_fbreg -0x10)
__vgic_v3_save_state:200.0 (vgic-v3-sr.c) Sbepe ║{
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc258 0xc3b0 (DW_OP_fbreg -0x10) __vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:199
+used_lrs var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc258 0xc3b0 (DW_OP_fbreg -0x18) __vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:201
~ 0000c258: d10143ff sub sp, sp, #0x50 <- 00003370(bl)<__vgic_v3_save_state>
~ 0000c25c: a9047bfd stp x29, x30, [sp, #64]
0000c258 CFA:r31 r29:u r30:u
~ 0000c260: 910103fd add x29, sp, #0x40
~ 0000c264: f81f03a0 stur x0, [x29, #-16]
__vgic_v3_save_state:201.17 (vgic-v3-sr.c) SbePe u64 used_lrs = ║cpu_if->used_lrs;
~ 0000c268: f85f03a8 ldur x8, [x29, #-16]
__vgic_v3_save_state:201.25 (vgic-v3-sr.c) sbepe u64 used_lrs = cpu_if->║used_lrs;
~ 0000c26c: b9413109 ldr w9, [x8, #304]
~ 0000c270: 2a0903e8 mov w8, w9
__vgic_v3_save_state:201.6 (vgic-v3-sr.c) sbepe u64 ║used_lrs = cpu_if->used_lrs;
~ 0000c274: f81e83a8 stur x8, [x29, #-24]
__vgic_v3_save_state:208.6 (vgic-v3-sr.c) Sbepe if (║used_lrs || !has_vhe()) {
~ 0000c278: f85e83a8 ldur x8, [x29, #-24]
__vgic_v3_save_state:208.15 (vgic-v3-sr.c) sbepe if (used_lrs ║|| !has_vhe()) {
~ ┌───0000c27c: b50000e8 cbnz x8, c298 <__vgic_v3_save_state+0x40>
│
~ │ ┌─0000c280: 14000001 b c284 <__vgic_v3_save_state+0x2c> <- 0000c27c(b.cc-succ)<fallthrough>
│ │
~ │ └>0000c284: 2a1f03e8 mov w8, wzr <- 0000c280(b)<__vgic_v3_save_state+0x2c>
c: 0xc288 0xc290 has_vhe inlined from __vgic_v3_save_state:208 (vgic-v3-sr.c) <997d8>:
c │ has_vhe:113.3 (virt.h) Sbepe ║return false;
~c │ 0000c288: 381ff3a8 sturb w8, [x29, #-1]
c │ has_vhe:116.1 (virt.h) Sbepe ║}
~c │ 0000c28c: 385ff3a8 ldurb w8, [x29, #-1]
│ __vgic_v3_save_state:208.6 (vgic-v3-sr.c) Sbepe if (║used_lrs || !has_vhe()) {
~ ┌──┼───0000c290: 37000148 tbnz w8, #0, c2b8 <__vgic_v3_save_state+0x60>
│ │
~ │ │ ┌─0000c294: 14000001 b c298 <__vgic_v3_save_state+0x40> <- 0000c290(b.cc-succ)<fallthrough>
│ │ │
│ │ │ __vgic_v3_save_state:209.8 (vgic-v3-sr.c) Sbepe if (!║cpu_if->vgic_sre) {
~ │ └>└>0000c298: f85f03a8 ldur x8, [x29, #-16] <- 0000c27c(b.cc)<__vgic_v3_save_state+0x40>,0000c294(b)<__vgic_v3_save_state+0x40>
│ __vgic_v3_save_state:209.16 (vgic-v3-sr.c) sbepe if (!cpu_if->║vgic_sre) {
~ │ 0000c29c: b9400909 ldr w9, [x8, #8]
│ __vgic_v3_save_state:209.7 (vgic-v3-sr.c) sbepe if (║!cpu_if->vgic_sre) {
~ │┌─────0000c2a0: 350000a9 cbnz w9, c2b4 <__vgic_v3_save_state+0x5c>
││
~ ││ ┌─0000c2a4: 14000001 b c2a8 <__vgic_v3_save_state+0x50> <- 0000c2a0(b.cc-succ)<fallthrough>
││ │
││ │ __vgic_v3_save_state:210.4 (vgic-v3-sr.c) Sbepe ║dsb(sy);
~ ││ └>0000c2a8: d5033f9f dsb sy <- 0000c2a4(b)<__vgic_v3_save_state+0x50>
││ __vgic_v3_save_state:211.4 (vgic-v3-sr.c) Sbepe ║isb();
~ ││ 0000c2ac: d5033fdf isb
││ __vgic_v3_save_state:212.3 (vgic-v3-sr.c) Sbepe }
~ ││ ┌─0000c2b0: 14000001 b c2b4 <__vgic_v3_save_state+0x5c>
││ │
││ │ __vgic_v3_save_state:213.2 (vgic-v3-sr.c) Sbepe }
~ │└>┌─└>0000c2b4: 14000001 b c2b8 <__vgic_v3_save_state+0x60> <- 0000c2a0(b.cc)<__vgic_v3_save_state+0x5c>,0000c2b0(b)<__vgic_v3_save_state+0x5c>
│ │
│ │ __vgic_v3_save_state:215.6 (vgic-v3-sr.c) Sbepe if (║used_lrs || cpu_if->its_vpe.its_vm) {
~ └─>└──>0000c2b8: f85e83a8 ldur x8, [x29, #-24] <- 0000c290(b.cc)<__vgic_v3_save_state+0x60>,0000c2b4(b)<__vgic_v3_save_state+0x60>
__vgic_v3_save_state:215.15 (vgic-v3-sr.c) sbepe if (used_lrs ║|| cpu_if->its_vpe.its_vm) {
~ ┌───0000c2bc: b50000c8 cbnz x8, c2d4 <__vgic_v3_save_state+0x7c>
│
~ │ ┌─0000c2c0: 14000001 b c2c4 <__vgic_v3_save_state+0x6c> <- 0000c2bc(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_save_state:215.18 (vgic-v3-sr.c) sbepe if (used_lrs || ║cpu_if->its_vpe.its_vm) {
~ │ └>0000c2c4: f85f03a8 ldur x8, [x29, #-16] <- 0000c2c0(b)<__vgic_v3_save_state+0x6c>
│ __vgic_v3_save_state:215.34 (vgic-v3-sr.c) sbepe if (used_lrs || cpu_if->its_vpe.║its_vm) {
~ │ 0000c2c8: f9405d08 ldr x8, [x8, #184]
│ __vgic_v3_save_state:215.6 (vgic-v3-sr.c) sbepe if (║used_lrs || cpu_if->its_vpe.its_vm) {
~ ┌──┼───0000c2cc: b40006c8 cbz x8, c3a4 <__vgic_v3_save_state+0x14c>
│ │
~ │ │ ┌─0000c2d0: 14000001 b c2d4 <__vgic_v3_save_state+0x7c> <- 0000c2cc(b.cc-succ)<fallthrough>
│ │ │
+i var int (base type, DW_ATE_signed size:4) 0xc2d4 0xc3a4 (DW_OP_fbreg -0x1c) lexblock:__vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:216
+elrsr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xc2d4 0xc3a4 (DW_OP_breg31 0x20) lexblock:__vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:217
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc2d4 0xc2e8 (DW_OP_breg31 0x18) lexblock:lexblock:__vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:219
~ │ └>└>0000c2d4: d53ccba8 mrs x8, s3_4_c12_c11_5 <- 0000c2bc(b.cc)<__vgic_v3_save_state+0x7c>,0000c2d0(b)<__vgic_v3_save_state+0x7c>
│ __vgic_v3_save_state:219.11 (vgic-v3-sr.c) Sbepe elrsr = ║read_gicreg(ICH_ELRSR_EL2);
~ │ 0000c2d8: f9000fe8 str x8, [sp, #24]
~ │ 0000c2dc: f9400fe8 ldr x8, [sp, #24]
~ │ 0000c2e0: f9000be8 str x8, [sp, #16]
~ │ 0000c2e4: f9400be8 ldr x8, [sp, #16]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc2d4 0xc2e8 (DW_OP_breg31 0x18) lexblock:lexblock:__vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:219
│ __vgic_v3_save_state:219.9 (vgic-v3-sr.c) sbepe elrsr ║= read_gicreg(ICH_ELRSR_EL2);
~ │ 0000c2e8: b90023e8 str w8, [sp, #32]
│ __vgic_v3_save_state:221.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EN, ICH_HCR_EL2);
~ │ ┌─0000c2ec: 14000001 b c2f0 <__vgic_v3_save_state+0x98>
│ │
│ │ __vgic_v3_save_state:221.3 (vgic-v3-sr.c) sbepe ║write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EN, ICH_HCR_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc2f0 0xc310 (DW_OP_breg31 0x8) lexblock:lexblock:__vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:221
~ │ └>0000c2f0: f85f03a8 ldur x8, [x29, #-16] <- 0000c2ec(b)<__vgic_v3_save_state+0x98>
~ │ 0000c2f4: b9400109 ldr w9, [x8]
~ │ 0000c2f8: 2a0903e8 mov w8, w9
~ │ 0000c2fc: 927f7908 and x8, x8, #0xfffffffe
~ │ 0000c300: f90007e8 str x8, [sp, #8]
~ │ 0000c304: f94007e8 ldr x8, [sp, #8]
~ │ 0000c308: d51ccb08 msr s3_4_c12_c11_0, x8
~ │ ┌─0000c30c: 14000001 b c310 <__vgic_v3_save_state+0xb8>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc2f0 0xc310 (DW_OP_breg31 0x8) lexblock:lexblock:__vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:221
│ │
~ │ └>0000c310: 2a1f03e8 mov w8, wzr <- 0000c30c(b)<__vgic_v3_save_state+0xb8>
│ __vgic_v3_save_state:223.10 (vgic-v3-sr.c) Sbepe for (i ║= 0; i < used_lrs; i++) {
~ │ 0000c314: b81e43a8 stur w8, [x29, #-28]
│ __vgic_v3_save_state:223.8 (vgic-v3-sr.c) sbepe for (║i = 0; i < used_lrs; i++) {
~ │ ┌─0000c318: 14000001 b c31c <__vgic_v3_save_state+0xc4>
│ │
│ │ __vgic_v3_save_state:223.15 (vgic-v3-sr.c) sbepe for (i = 0; ║i < used_lrs; i++) {
~ │╔══>└>0000c31c: b89e43a8 ldursw x8, [x29, #-28] <- 0000c318(b)<__vgic_v3_save_state+0xc4>,v0000c39c(b)<__vgic_v3_save_state+0xc4>
│║ __vgic_v3_save_state:223.19 (vgic-v3-sr.c) sbepe for (i = 0; i < ║used_lrs; i++) {
~ │║ 0000c320: f85e83a9 ldur x9, [x29, #-24]
│║ __vgic_v3_save_state:223.3 (vgic-v3-sr.c) sbepe ║for (i = 0; i < used_lrs; i++) {
~ │║ 0000c324: eb090108 subs x8, x8, x9
~ │║┌────0000c328: 540003c2 b.cs c3a0 <__vgic_v3_save_state+0x148> // b.hs, b.nlast
│║│
~ │║│ ┌─0000c32c: 14000001 b c330 <__vgic_v3_save_state+0xd8> <- 0000c328(b.cc-succ)<fallthrough>
│║│ │
│║│ │ __vgic_v3_save_state:224.8 (vgic-v3-sr.c) Sbepe if (║elrsr & (1 << i))
~ │║│ └>0000c330: b94023e8 ldr w8, [sp, #32] <- 0000c32c(b)<__vgic_v3_save_state+0xd8>
│║│ __vgic_v3_save_state:224.22 (vgic-v3-sr.c) sbepe if (elrsr & (1 << ║i))
~ │║│ 0000c334: b85e43a9 ldur w9, [x29, #-28]
~ │║│ 0000c338: 2a0903e0 mov w0, w9
│║│ __vgic_v3_save_state:224.8 (vgic-v3-sr.c) sbepe if (║elrsr & (1 << i))
~ │║│ 0000c33c: 1ac02508 lsr w8, w8, w0
~ │║│ ┌──0000c340: 36000128 tbz w8, #0, c364 <__vgic_v3_save_state+0x10c>
│║│ │
~ │║│ │┌─0000c344: 14000001 b c348 <__vgic_v3_save_state+0xf0> <- 0000c340(b.cc-succ)<fallthrough>
│║│ ││
│║│ ││ __vgic_v3_save_state:225.5 (vgic-v3-sr.c) Sbepe ║cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
~ │║│ │└>0000c348: f85f03a8 ldur x8, [x29, #-16] <- 0000c344(b)<__vgic_v3_save_state+0xf0>
│║│ │ __vgic_v3_save_state:225.21 (vgic-v3-sr.c) sbepe cpu_if->vgic_lr[║i] &= ~ICH_LR_STATE;
~ │║│ │ 0000c34c: b89e43a9 ldursw x9, [x29, #-28]
│║│ │ __vgic_v3_save_state:225.13 (vgic-v3-sr.c) sbepe cpu_if->║vgic_lr[i] &= ~ICH_LR_STATE;
~ │║│ │ 0000c350: 8b090d08 add x8, x8, x9, lsl #3
│║│ │ __vgic_v3_save_state:225.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_lr[i] ║&= ~ICH_LR_STATE;
~ │║│ │ 0000c354: f9401909 ldr x9, [x8, #48]
~ │║│ │ 0000c358: 9240f529 and x9, x9, #0x3fffffffffffffff
~ │║│ │ 0000c35c: f9001909 str x9, [x8, #48]
│║│ │ __vgic_v3_save_state:225.5 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
~ │║│┌┼──0000c360: 14000008 b c380 <__vgic_v3_save_state+0x128>
│║│││
│║│││ __vgic_v3_save_state:227.42 (vgic-v3-sr.c) Sbepe cpu_if->vgic_lr[i] = __gic_v3_get_lr(║i);
~ │║││└─>0000c364: b85e43a0 ldur w0, [x29, #-28] <- 0000c340(b.cc)<__vgic_v3_save_state+0x10c>
│║││ __vgic_v3_save_state:227.26 (vgic-v3-sr.c) sbepe cpu_if->vgic_lr[i] = ║__gic_v3_get_lr(i);
~ │║││ 0000c368: 94000012 bl c3b0 <__gic_v3_get_lr>
│║││
│║││ __vgic_v3_save_state:227.5 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
~ │║││ 0000c36c: f85f03a8 ldur x8, [x29, #-16] <- 0000c368(bl-succ)<return>
│║││ __vgic_v3_save_state:227.21 (vgic-v3-sr.c) sbepe cpu_if->vgic_lr[║i] = __gic_v3_get_lr(i);
~ │║││ 0000c370: b89e43a9 ldursw x9, [x29, #-28]
│║││ __vgic_v3_save_state:227.13 (vgic-v3-sr.c) sbepe cpu_if->║vgic_lr[i] = __gic_v3_get_lr(i);
~ │║││ 0000c374: 8b090d08 add x8, x8, x9, lsl #3
│║││ __vgic_v3_save_state:227.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_lr[i] ║= __gic_v3_get_lr(i);
~ │║││ 0000c378: f9001900 str x0, [x8, #48]
~ │║││ ┌─0000c37c: 14000001 b c380 <__vgic_v3_save_state+0x128>
│║││ │
│║││ │ __vgic_v3_save_state:229.23 (vgic-v3-sr.c) Sbepe __gic_v3_set_lr(0, ║i);
~ │║│└>└>0000c380: b85e43a1 ldur w1, [x29, #-28] <- 0000c360(b)<__vgic_v3_save_state+0x128>,0000c37c(b)<__vgic_v3_save_state+0x128>
~ │║│ 0000c384: aa1f03e0 mov x0, xzr
│║│ __vgic_v3_save_state:229.4 (vgic-v3-sr.c) sbepe ║__gic_v3_set_lr(0, i);
~ │║│ 0000c388: 9400008f bl c5c4 <__gic_v3_set_lr>
│║│
│║│ __vgic_v3_save_state:230.3 (vgic-v3-sr.c) Sbepe }
~ │║│ ┌─0000c38c: 14000001 b c390 <__vgic_v3_save_state+0x138> <- 0000c388(bl-succ)<return>
│║│ │
│║│ │ __vgic_v3_save_state:223.30 (vgic-v3-sr.c) Sbepe for (i = 0; i < used_lrs; i║++) {
~ │║│ └>0000c390: b85e43a8 ldur w8, [x29, #-28] <- 0000c38c(b)<__vgic_v3_save_state+0x138>
~ │║│ 0000c394: 11000508 add w8, w8, #0x1
~ │║│ 0000c398: b81e43a8 stur w8, [x29, #-28]
│║│ __vgic_v3_save_state:223.3 (vgic-v3-sr.c) sbepe ║for (i = 0; i < used_lrs; i++) {
~ │╚╪════0000c39c: 17ffffe0 b c31c <__vgic_v3_save_state+0xc4>
│ │
│ │ __vgic_v3_save_state:231.2 (vgic-v3-sr.c) Sbepe }
~ │ └─>┌─0000c3a0: 14000001 b c3a4 <__vgic_v3_save_state+0x14c> <- 0000c328(b.cc)<__vgic_v3_save_state+0x148>
-i var int (base type, DW_ATE_signed size:4) 0xc2d4 0xc3a4 (DW_OP_fbreg -0x1c) lexblock:__vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:216
-elrsr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xc2d4 0xc3a4 (DW_OP_breg31 0x20) lexblock:__vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:217
│ │
│ │ __vgic_v3_save_state:232.1 (vgic-v3-sr.c) Sbepe ║}
~ └───>└>0000c3a4: a9447bfd ldp x29, x30, [sp, #64] <- 0000c2cc(b.cc)<__vgic_v3_save_state+0x14c>,0000c3a0(b)<__vgic_v3_save_state+0x14c>
~ 0000c3a8: 910143ff add sp, sp, #0x50
0000c264 CFA:r29+16 r29:c-16 r30:c-8
~ 0000c3ac: d65f03c0 ret
-cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc258 0xc3b0 (DW_OP_fbreg -0x10) __vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:199
-used_lrs var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc258 0xc3b0 (DW_OP_fbreg -0x18) __vgic_v3_save_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:201
**0000c3b0 <__gic_v3_get_lr>:
+ __gic_v3_get_lr params:
+lr param unsigned int (base type, DW_ATE_unsigned size:4) 0xc3b0 0xc5c4 (DW_OP_fbreg 0x114)
__gic_v3_get_lr:22.0 (vgic-v3-sr.c) Sbepe ║{
+lr param unsigned int (base type, DW_ATE_unsigned size:4) 0xc3b0 0xc5c4 (DW_OP_fbreg 0x114) __gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:21
~ 0000c3b0: d104c3ff sub sp, sp, #0x130 <- 0000c368(bl)<__gic_v3_get_lr>,0000e7f0(bl)<__gic_v3_get_lr>,0000edf8(bl)<__gic_v3_get_lr>
0000c3b0 CFA:r31 r29:u
~ 0000c3b4: f90093fd str x29, [sp, #288]
~ 0000c3b8: b90117e0 str w0, [sp, #276]
__gic_v3_get_lr:23.10 (vgic-v3-sr.c) SbePe switch (║lr & 0xf) {
~ 0000c3bc: b94117e8 ldr w8, [sp, #276]
~ 0000c3c0: 2a0803e9 mov w9, w8
__gic_v3_get_lr:23.2 (vgic-v3-sr.c) sbepe ║switch (lr & 0xf) {
~ 0000c3c4: 92400d29 and x9, x9, #0xf
~ 0000c3c8: 2a0903e8 mov w8, w9
~ 0000c3cc: 71003d08 subs w8, w8, #0xf
~ 0000c3d0: f90007e9 str x9, [sp, #8]
~ ┌────0000c3d4: 54000ee8 b.hi c5b0 <__gic_v3_get_lr+0x200> // b.pmore
│
~ │ 0000c3d8: f0000048 adrp x8, 17000 <___kvm_hyp_init+0x3c> <- 0000c3d4(b.cc-succ)<fallthrough>
~ │ 0000c3dc: 913b3108 add x8, x8, #0xecc
~ │ 0000c3e0: f94007eb ldr x11, [sp, #8]
~ │ 0000c3e4: b8ab790a ldrsw x10, [x8, x11, lsl #2]
~ │ 0000c3e8: 8b0a0109 add x9, x8, x10
│
~ │ X0000c3ec: d61f0120 br x9 -> 0000c3ec<indirect0> <- 0000c3ec(br)<indirect0>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc3f0 0xc404 (DW_OP_fbreg 0x108) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:25
~ │ 0000c3f0: d53ccc08 mrs x8, s3_4_c12_c12_0
│ __gic_v3_get_lr:25.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR0_EL2);
~ │ 0000c3f4: f90087e8 str x8, [sp, #264]
~ │ 0000c3f8: f94087e8 ldr x8, [sp, #264]
~ │ 0000c3fc: f90083e8 str x8, [sp, #256]
~ │ 0000c400: f94083e8 ldr x8, [sp, #256]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc3f0 0xc404 (DW_OP_fbreg 0x108) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:25
│ __gic_v3_get_lr:25.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR0_EL2);
~ │ 0000c404: f9008fe8 str x8, [sp, #280]
~ ┌────────────────────────────┼────0000c408: 1400006b b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc40c 0xc420 (DW_OP_fbreg 0xf8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:27
~ │ │ 0000c40c: d53ccc28 mrs x8, s3_4_c12_c12_1
│ │ __gic_v3_get_lr:27.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR1_EL2);
~ │ │ 0000c410: f9007fe8 str x8, [sp, #248]
~ │ │ 0000c414: f9407fe8 ldr x8, [sp, #248]
~ │ │ 0000c418: f9007be8 str x8, [sp, #240]
~ │ │ 0000c41c: f9407be8 ldr x8, [sp, #240]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc40c 0xc420 (DW_OP_fbreg 0xf8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:27
│ │ __gic_v3_get_lr:27.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR1_EL2);
~ │ │ 0000c420: f9008fe8 str x8, [sp, #280]
~ │ ┌──────────────────────────┼────0000c424: 14000064 b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc428 0xc43c (DW_OP_fbreg 0xe8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:29
~ │ │ │ 0000c428: d53ccc48 mrs x8, s3_4_c12_c12_2
│ │ │ __gic_v3_get_lr:29.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR2_EL2);
~ │ │ │ 0000c42c: f90077e8 str x8, [sp, #232]
~ │ │ │ 0000c430: f94077e8 ldr x8, [sp, #232]
~ │ │ │ 0000c434: f90073e8 str x8, [sp, #224]
~ │ │ │ 0000c438: f94073e8 ldr x8, [sp, #224]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc428 0xc43c (DW_OP_fbreg 0xe8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:29
│ │ │ __gic_v3_get_lr:29.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR2_EL2);
~ │ │ │ 0000c43c: f9008fe8 str x8, [sp, #280]
~ │ │ ┌────────────────────────┼────0000c440: 1400005d b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc444 0xc458 (DW_OP_fbreg 0xd8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:31
~ │ │ │ │ 0000c444: d53ccc68 mrs x8, s3_4_c12_c12_3
│ │ │ │ __gic_v3_get_lr:31.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR3_EL2);
~ │ │ │ │ 0000c448: f9006fe8 str x8, [sp, #216]
~ │ │ │ │ 0000c44c: f9406fe8 ldr x8, [sp, #216]
~ │ │ │ │ 0000c450: f9006be8 str x8, [sp, #208]
~ │ │ │ │ 0000c454: f9406be8 ldr x8, [sp, #208]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc444 0xc458 (DW_OP_fbreg 0xd8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:31
│ │ │ │ __gic_v3_get_lr:31.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR3_EL2);
~ │ │ │ │ 0000c458: f9008fe8 str x8, [sp, #280]
~ │ │ │ ┌──────────────────────┼────0000c45c: 14000056 b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc460 0xc474 (DW_OP_fbreg 0xc8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:33
~ │ │ │ │ │ 0000c460: d53ccc88 mrs x8, s3_4_c12_c12_4
│ │ │ │ │ __gic_v3_get_lr:33.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR4_EL2);
~ │ │ │ │ │ 0000c464: f90067e8 str x8, [sp, #200]
~ │ │ │ │ │ 0000c468: f94067e8 ldr x8, [sp, #200]
~ │ │ │ │ │ 0000c46c: f90063e8 str x8, [sp, #192]
~ │ │ │ │ │ 0000c470: f94063e8 ldr x8, [sp, #192]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc460 0xc474 (DW_OP_fbreg 0xc8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:33
│ │ │ │ │ __gic_v3_get_lr:33.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR4_EL2);
~ │ │ │ │ │ 0000c474: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ ┌────────────────────┼────0000c478: 1400004f b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc47c 0xc490 (DW_OP_fbreg 0xb8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:35
~ │ │ │ │ │ │ 0000c47c: d53ccca8 mrs x8, s3_4_c12_c12_5
│ │ │ │ │ │ __gic_v3_get_lr:35.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR5_EL2);
~ │ │ │ │ │ │ 0000c480: f9005fe8 str x8, [sp, #184]
~ │ │ │ │ │ │ 0000c484: f9405fe8 ldr x8, [sp, #184]
~ │ │ │ │ │ │ 0000c488: f9005be8 str x8, [sp, #176]
~ │ │ │ │ │ │ 0000c48c: f9405be8 ldr x8, [sp, #176]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc47c 0xc490 (DW_OP_fbreg 0xb8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:35
│ │ │ │ │ │ __gic_v3_get_lr:35.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR5_EL2);
~ │ │ │ │ │ │ 0000c490: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ ┌──────────────────┼────0000c494: 14000048 b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc498 0xc4ac (DW_OP_fbreg 0xa8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:37
~ │ │ │ │ │ │ │ 0000c498: d53cccc8 mrs x8, s3_4_c12_c12_6
│ │ │ │ │ │ │ __gic_v3_get_lr:37.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR6_EL2);
~ │ │ │ │ │ │ │ 0000c49c: f90057e8 str x8, [sp, #168]
~ │ │ │ │ │ │ │ 0000c4a0: f94057e8 ldr x8, [sp, #168]
~ │ │ │ │ │ │ │ 0000c4a4: f90053e8 str x8, [sp, #160]
~ │ │ │ │ │ │ │ 0000c4a8: f94053e8 ldr x8, [sp, #160]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc498 0xc4ac (DW_OP_fbreg 0xa8) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:37
│ │ │ │ │ │ │ __gic_v3_get_lr:37.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR6_EL2);
~ │ │ │ │ │ │ │ 0000c4ac: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ ┌────────────────┼────0000c4b0: 14000041 b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc4b4 0xc4c8 (DW_OP_fbreg 0x98) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:39
~ │ │ │ │ │ │ │ │ 0000c4b4: d53ccce8 mrs x8, s3_4_c12_c12_7
│ │ │ │ │ │ │ │ __gic_v3_get_lr:39.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR7_EL2);
~ │ │ │ │ │ │ │ │ 0000c4b8: f9004fe8 str x8, [sp, #152]
~ │ │ │ │ │ │ │ │ 0000c4bc: f9404fe8 ldr x8, [sp, #152]
~ │ │ │ │ │ │ │ │ 0000c4c0: f9004be8 str x8, [sp, #144]
~ │ │ │ │ │ │ │ │ 0000c4c4: f9404be8 ldr x8, [sp, #144]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc4b4 0xc4c8 (DW_OP_fbreg 0x98) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:39
│ │ │ │ │ │ │ │ __gic_v3_get_lr:39.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR7_EL2);
~ │ │ │ │ │ │ │ │ 0000c4c8: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ │ ┌──────────────┼────0000c4cc: 1400003a b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc4d0 0xc4e4 (DW_OP_fbreg 0x88) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:41
~ │ │ │ │ │ │ │ │ │ 0000c4d0: d53ccd08 mrs x8, s3_4_c12_c13_0
│ │ │ │ │ │ │ │ │ __gic_v3_get_lr:41.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR8_EL2);
~ │ │ │ │ │ │ │ │ │ 0000c4d4: f90047e8 str x8, [sp, #136]
~ │ │ │ │ │ │ │ │ │ 0000c4d8: f94047e8 ldr x8, [sp, #136]
~ │ │ │ │ │ │ │ │ │ 0000c4dc: f90043e8 str x8, [sp, #128]
~ │ │ │ │ │ │ │ │ │ 0000c4e0: f94043e8 ldr x8, [sp, #128]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc4d0 0xc4e4 (DW_OP_fbreg 0x88) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:41
│ │ │ │ │ │ │ │ │ __gic_v3_get_lr:41.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR8_EL2);
~ │ │ │ │ │ │ │ │ │ 0000c4e4: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ │ │ ┌────────────┼────0000c4e8: 14000033 b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc4ec 0xc500 (DW_OP_fbreg 0x78) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:43
~ │ │ │ │ │ │ │ │ │ │ 0000c4ec: d53ccd28 mrs x8, s3_4_c12_c13_1
│ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:43.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR9_EL2);
~ │ │ │ │ │ │ │ │ │ │ 0000c4f0: f9003fe8 str x8, [sp, #120]
~ │ │ │ │ │ │ │ │ │ │ 0000c4f4: f9403fe8 ldr x8, [sp, #120]
~ │ │ │ │ │ │ │ │ │ │ 0000c4f8: f9003be8 str x8, [sp, #112]
~ │ │ │ │ │ │ │ │ │ │ 0000c4fc: f9403be8 ldr x8, [sp, #112]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc4ec 0xc500 (DW_OP_fbreg 0x78) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:43
│ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:43.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR9_EL2);
~ │ │ │ │ │ │ │ │ │ │ 0000c500: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ │ │ │ ┌──────────┼────0000c504: 1400002c b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc508 0xc51c (DW_OP_fbreg 0x68) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:45
~ │ │ │ │ │ │ │ │ │ │ │ 0000c508: d53ccd48 mrs x8, s3_4_c12_c13_2
│ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:45.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR10_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ 0000c50c: f90037e8 str x8, [sp, #104]
~ │ │ │ │ │ │ │ │ │ │ │ 0000c510: f94037e8 ldr x8, [sp, #104]
~ │ │ │ │ │ │ │ │ │ │ │ 0000c514: f90033e8 str x8, [sp, #96]
~ │ │ │ │ │ │ │ │ │ │ │ 0000c518: f94033e8 ldr x8, [sp, #96]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc508 0xc51c (DW_OP_fbreg 0x68) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:45
│ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:45.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR10_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ 0000c51c: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ │ │ │ │ ┌────────┼────0000c520: 14000025 b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc524 0xc538 (DW_OP_fbreg 0x58) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:47
~ │ │ │ │ │ │ │ │ │ │ │ │ 0000c524: d53ccd68 mrs x8, s3_4_c12_c13_3
│ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:47.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR11_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ 0000c528: f9002fe8 str x8, [sp, #88]
~ │ │ │ │ │ │ │ │ │ │ │ │ 0000c52c: f9402fe8 ldr x8, [sp, #88]
~ │ │ │ │ │ │ │ │ │ │ │ │ 0000c530: f9002be8 str x8, [sp, #80]
~ │ │ │ │ │ │ │ │ │ │ │ │ 0000c534: f9402be8 ldr x8, [sp, #80]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc524 0xc538 (DW_OP_fbreg 0x58) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:47
│ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:47.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR11_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ 0000c538: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ │ │ │ │ │ ┌──────┼────0000c53c: 1400001e b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc540 0xc554 (DW_OP_fbreg 0x48) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:49
~ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c540: d53ccd88 mrs x8, s3_4_c12_c13_4
│ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:49.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR12_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c544: f90027e8 str x8, [sp, #72]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c548: f94027e8 ldr x8, [sp, #72]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c54c: f90023e8 str x8, [sp, #64]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c550: f94023e8 ldr x8, [sp, #64]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc540 0xc554 (DW_OP_fbreg 0x48) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:49
│ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:49.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR12_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c554: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ │ │ │ │ │ │ ┌────┼────0000c558: 14000017 b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc55c 0xc570 (DW_OP_fbreg 0x38) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:51
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c55c: d53ccda8 mrs x8, s3_4_c12_c13_5
│ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:51.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR13_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c560: f9001fe8 str x8, [sp, #56]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c564: f9401fe8 ldr x8, [sp, #56]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c568: f9001be8 str x8, [sp, #48]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c56c: f9401be8 ldr x8, [sp, #48]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc55c 0xc570 (DW_OP_fbreg 0x38) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:51
│ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:51.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR13_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c570: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌──┼────0000c574: 14000010 b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc578 0xc58c (DW_OP_fbreg 0x28) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:53
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c578: d53ccdc8 mrs x8, s3_4_c12_c13_6
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:53.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR14_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c57c: f90017e8 str x8, [sp, #40]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c580: f94017e8 ldr x8, [sp, #40]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c584: f90013e8 str x8, [sp, #32]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c588: f94013e8 ldr x8, [sp, #32]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc578 0xc58c (DW_OP_fbreg 0x28) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:53
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:53.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR14_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c58c: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌┼────0000c590: 14000009 b c5b4 <__gic_v3_get_lr+0x204>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc594 0xc5a8 (DW_OP_fbreg 0x18) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:55
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ││ 0000c594: d53ccde8 mrs x8, s3_4_c12_c13_7
│ │ │ │ │ │ │ │ │ │ │ │ │ │ ││ __gic_v3_get_lr:55.10 (vgic-v3-sr.c) Sbepe return ║read_gicreg(ICH_LR15_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ││ 0000c598: f9000fe8 str x8, [sp, #24]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ││ 0000c59c: f9400fe8 ldr x8, [sp, #24]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ││ 0000c5a0: f9000be8 str x8, [sp, #16]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ││ 0000c5a4: f9400be8 ldr x8, [sp, #16]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc594 0xc5a8 (DW_OP_fbreg 0x18) lexblock:__gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:55
│ │ │ │ │ │ │ │ │ │ │ │ │ │ ││ __gic_v3_get_lr:55.3 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_LR15_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ││ 0000c5a8: f9008fe8 str x8, [sp, #280]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ││┌───0000c5ac: 14000002 b c5b4 <__gic_v3_get_lr+0x204>
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │││
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │││ __gic_v3_get_lr:58.2 (vgic-v3-sr.c) Sbepe ║unreachable();
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │└┼>┌─0000c5b0: 14000001 b c5b4 <__gic_v3_get_lr+0x204> <- 0000c3d4(b.cc)<__gic_v3_get_lr+0x200>
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_get_lr:59.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>└>└>└>└>└>└>└>└>└>└>└>└>└>└>└>0000c5b4: f9408fe0 ldr x0, [sp, #280] <- 0000c408(b)<__gic_v3_get_lr+0x204>,0000c424(b)<__gic_v3_get_lr+0x204>,0000c440(b)<__gic_v3_get_lr+0x204>,0000c45c(b)<__gic_v3_get_lr+0x204>,0000c478(b)<__gic_v3_get_lr+0x204>,0000c494(b)<__gic_v3_get_lr+0x204>,0000c4b0(b)<__gic_v3_get_lr+0x204>,0000c4cc(b)<__gic_v3_get_lr+0x204>,0000c4e8(b)<__gic_v3_get_lr+0x204>,0000c504(b)<__gic_v3_get_lr+0x204>,0000c520(b)<__gic_v3_get_lr+0x204>,0000c53c(b)<__gic_v3_get_lr+0x204>,0000c558(b)<__gic_v3_get_lr+0x204>,0000c574(b)<__gic_v3_get_lr+0x204>,0000c590(b)<__gic_v3_get_lr+0x204>,0000c5ac(b)<__gic_v3_get_lr+0x204>,0000c5b0(b)<__gic_v3_get_lr+0x204>
~ 0000c5b8: f94093fd ldr x29, [sp, #288]
~ 0000c5bc: 9104c3ff add sp, sp, #0x130
0000c3b8 CFA:r31+304 r29:c-16
~ 0000c5c0: d65f03c0 ret
-lr param unsigned int (base type, DW_ATE_unsigned size:4) 0xc3b0 0xc5c4 (DW_OP_fbreg 0x114) __gic_v3_get_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:21
**0000c5c4 <__gic_v3_set_lr>:
+ __gic_v3_set_lr params:
+val param typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc5c4 0xc7cc (DW_OP_fbreg 0x98)
+lr param int (base type, DW_ATE_signed size:4) 0xc5c4 0xc7cc (DW_OP_fbreg 0x94)
__gic_v3_set_lr:62.0 (vgic-v3-sr.c) Sbepe ║{
0000c5c4 CFA:r31
+val param typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc5c4 0xc7cc (DW_OP_fbreg 0x98) __gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:61
+lr param int (base type, DW_ATE_signed size:4) 0xc5c4 0xc7cc (DW_OP_fbreg 0x94) __gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:61
~ 0000c5c4: d10283ff sub sp, sp, #0xa0 <- 0000c388(bl)<__gic_v3_set_lr>,0000c85c(bl)<__gic_v3_set_lr>,0000d080(bl)<__gic_v3_set_lr>,0000d920(bl)<__gic_v3_set_lr>,0000ef30(bl)<__gic_v3_set_lr>
~ 0000c5c8: f9004fe0 str x0, [sp, #152]
~ 0000c5cc: b90097e1 str w1, [sp, #148]
__gic_v3_set_lr:63.10 (vgic-v3-sr.c) SbePe switch (║lr & 0xf) {
~ 0000c5d0: b94097e8 ldr w8, [sp, #148]
~ 0000c5d4: 2a0803e9 mov w9, w8
__gic_v3_set_lr:63.2 (vgic-v3-sr.c) sbepe ║switch (lr & 0xf) {
~ 0000c5d8: 92400d29 and x9, x9, #0xf
~ 0000c5dc: 2a0903e8 mov w8, w9
~ 0000c5e0: 71003d08 subs w8, w8, #0xf
~ 0000c5e4: f90007e9 str x9, [sp, #8]
~ ┌───────────────────────────────────0000c5e8: 54000ee8 b.hi c7c4 <__gic_v3_set_lr+0x200> // b.pmore
│
~ │ 0000c5ec: f0000048 adrp x8, 17000 <___kvm_hyp_init+0x3c> <- 0000c5e8(b.cc-succ)<fallthrough>
~ │ 0000c5f0: 913c3108 add x8, x8, #0xf0c
~ │ 0000c5f4: f94007eb ldr x11, [sp, #8]
~ │ 0000c5f8: b8ab790a ldrsw x10, [x8, x11, lsl #2]
~ │ 0000c5fc: 8b0a0109 add x9, x8, x10
│
~ │ X0000c600: d61f0120 br x9 -> 0000c600<indirect0> <- 0000c600(br)<indirect0>
│ __gic_v3_set_lr:65.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR0_EL2);
~ │ ┌─0000c604: 14000001 b c608 <__gic_v3_set_lr+0x44>
│ │
│ │ __gic_v3_set_lr:65.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR0_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc608 0xc61c (DW_OP_fbreg 0x88) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:65
~ │ └>0000c608: f9404fe8 ldr x8, [sp, #152] <- 0000c604(b)<__gic_v3_set_lr+0x44>
~ │ 0000c60c: f90047e8 str x8, [sp, #136]
~ │ 0000c610: f94047e8 ldr x8, [sp, #136]
~ │ 0000c614: d51ccc08 msr s3_4_c12_c12_0, x8
~ │ ┌─0000c618: 14000001 b c61c <__gic_v3_set_lr+0x58>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc608 0xc61c (DW_OP_fbreg 0x88) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:65
│ │
│ │ __gic_v3_set_lr:66.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ ┌───────────────────────────────└>0000c61c: 1400006a b c7c4 <__gic_v3_set_lr+0x200> <- 0000c618(b)<__gic_v3_set_lr+0x58>
│ │ __gic_v3_set_lr:68.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR1_EL2);
~ │ │ ┌─0000c620: 14000001 b c624 <__gic_v3_set_lr+0x60>
│ │ │
│ │ │ __gic_v3_set_lr:68.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR1_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc624 0xc638 (DW_OP_fbreg 0x80) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:68
~ │ │ └>0000c624: f9404fe8 ldr x8, [sp, #152] <- 0000c620(b)<__gic_v3_set_lr+0x60>
~ │ │ 0000c628: f90043e8 str x8, [sp, #128]
~ │ │ 0000c62c: f94043e8 ldr x8, [sp, #128]
~ │ │ 0000c630: d51ccc28 msr s3_4_c12_c12_1, x8
~ │ │ ┌─0000c634: 14000001 b c638 <__gic_v3_set_lr+0x74>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc624 0xc638 (DW_OP_fbreg 0x80) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:68
│ │ │
│ │ │ __gic_v3_set_lr:69.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ┌─────────────────────────────└>0000c638: 14000063 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c634(b)<__gic_v3_set_lr+0x74>
│ │ │ __gic_v3_set_lr:71.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR2_EL2);
~ │ │ │ ┌─0000c63c: 14000001 b c640 <__gic_v3_set_lr+0x7c>
│ │ │ │
│ │ │ │ __gic_v3_set_lr:71.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR2_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc640 0xc654 (DW_OP_fbreg 0x78) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:71
~ │ │ │ └>0000c640: f9404fe8 ldr x8, [sp, #152] <- 0000c63c(b)<__gic_v3_set_lr+0x7c>
~ │ │ │ 0000c644: f9003fe8 str x8, [sp, #120]
~ │ │ │ 0000c648: f9403fe8 ldr x8, [sp, #120]
~ │ │ │ 0000c64c: d51ccc48 msr s3_4_c12_c12_2, x8
~ │ │ │ ┌─0000c650: 14000001 b c654 <__gic_v3_set_lr+0x90>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc640 0xc654 (DW_OP_fbreg 0x78) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:71
│ │ │ │
│ │ │ │ __gic_v3_set_lr:72.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ ┌───────────────────────────└>0000c654: 1400005c b c7c4 <__gic_v3_set_lr+0x200> <- 0000c650(b)<__gic_v3_set_lr+0x90>
│ │ │ │ __gic_v3_set_lr:74.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR3_EL2);
~ │ │ │ │ ┌─0000c658: 14000001 b c65c <__gic_v3_set_lr+0x98>
│ │ │ │ │
│ │ │ │ │ __gic_v3_set_lr:74.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR3_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc65c 0xc670 (DW_OP_fbreg 0x70) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:74
~ │ │ │ │ └>0000c65c: f9404fe8 ldr x8, [sp, #152] <- 0000c658(b)<__gic_v3_set_lr+0x98>
~ │ │ │ │ 0000c660: f9003be8 str x8, [sp, #112]
~ │ │ │ │ 0000c664: f9403be8 ldr x8, [sp, #112]
~ │ │ │ │ 0000c668: d51ccc68 msr s3_4_c12_c12_3, x8
~ │ │ │ │ ┌─0000c66c: 14000001 b c670 <__gic_v3_set_lr+0xac>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc65c 0xc670 (DW_OP_fbreg 0x70) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:74
│ │ │ │ │
│ │ │ │ │ __gic_v3_set_lr:75.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ ┌─────────────────────────└>0000c670: 14000055 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c66c(b)<__gic_v3_set_lr+0xac>
│ │ │ │ │ __gic_v3_set_lr:77.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR4_EL2);
~ │ │ │ │ │ ┌─0000c674: 14000001 b c678 <__gic_v3_set_lr+0xb4>
│ │ │ │ │ │
│ │ │ │ │ │ __gic_v3_set_lr:77.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR4_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc678 0xc68c (DW_OP_fbreg 0x68) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:77
~ │ │ │ │ │ └>0000c678: f9404fe8 ldr x8, [sp, #152] <- 0000c674(b)<__gic_v3_set_lr+0xb4>
~ │ │ │ │ │ 0000c67c: f90037e8 str x8, [sp, #104]
~ │ │ │ │ │ 0000c680: f94037e8 ldr x8, [sp, #104]
~ │ │ │ │ │ 0000c684: d51ccc88 msr s3_4_c12_c12_4, x8
~ │ │ │ │ │ ┌─0000c688: 14000001 b c68c <__gic_v3_set_lr+0xc8>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc678 0xc68c (DW_OP_fbreg 0x68) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:77
│ │ │ │ │ │
│ │ │ │ │ │ __gic_v3_set_lr:78.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ ┌───────────────────────└>0000c68c: 1400004e b c7c4 <__gic_v3_set_lr+0x200> <- 0000c688(b)<__gic_v3_set_lr+0xc8>
│ │ │ │ │ │ __gic_v3_set_lr:80.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR5_EL2);
~ │ │ │ │ │ │ ┌─0000c690: 14000001 b c694 <__gic_v3_set_lr+0xd0>
│ │ │ │ │ │ │
│ │ │ │ │ │ │ __gic_v3_set_lr:80.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR5_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc694 0xc6a8 (DW_OP_fbreg 0x60) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:80
~ │ │ │ │ │ │ └>0000c694: f9404fe8 ldr x8, [sp, #152] <- 0000c690(b)<__gic_v3_set_lr+0xd0>
~ │ │ │ │ │ │ 0000c698: f90033e8 str x8, [sp, #96]
~ │ │ │ │ │ │ 0000c69c: f94033e8 ldr x8, [sp, #96]
~ │ │ │ │ │ │ 0000c6a0: d51ccca8 msr s3_4_c12_c12_5, x8
~ │ │ │ │ │ │ ┌─0000c6a4: 14000001 b c6a8 <__gic_v3_set_lr+0xe4>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc694 0xc6a8 (DW_OP_fbreg 0x60) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:80
│ │ │ │ │ │ │
│ │ │ │ │ │ │ __gic_v3_set_lr:81.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ ┌─────────────────────└>0000c6a8: 14000047 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c6a4(b)<__gic_v3_set_lr+0xe4>
│ │ │ │ │ │ │ __gic_v3_set_lr:83.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR6_EL2);
~ │ │ │ │ │ │ │ ┌─0000c6ac: 14000001 b c6b0 <__gic_v3_set_lr+0xec>
│ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ __gic_v3_set_lr:83.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR6_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc6b0 0xc6c4 (DW_OP_fbreg 0x58) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:83
~ │ │ │ │ │ │ │ └>0000c6b0: f9404fe8 ldr x8, [sp, #152] <- 0000c6ac(b)<__gic_v3_set_lr+0xec>
~ │ │ │ │ │ │ │ 0000c6b4: f9002fe8 str x8, [sp, #88]
~ │ │ │ │ │ │ │ 0000c6b8: f9402fe8 ldr x8, [sp, #88]
~ │ │ │ │ │ │ │ 0000c6bc: d51cccc8 msr s3_4_c12_c12_6, x8
~ │ │ │ │ │ │ │ ┌─0000c6c0: 14000001 b c6c4 <__gic_v3_set_lr+0x100>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc6b0 0xc6c4 (DW_OP_fbreg 0x58) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:83
│ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ __gic_v3_set_lr:84.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ ┌───────────────────└>0000c6c4: 14000040 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c6c0(b)<__gic_v3_set_lr+0x100>
│ │ │ │ │ │ │ │ __gic_v3_set_lr:86.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR7_EL2);
~ │ │ │ │ │ │ │ │ ┌─0000c6c8: 14000001 b c6cc <__gic_v3_set_lr+0x108>
│ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ __gic_v3_set_lr:86.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR7_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc6cc 0xc6e0 (DW_OP_fbreg 0x50) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:86
~ │ │ │ │ │ │ │ │ └>0000c6cc: f9404fe8 ldr x8, [sp, #152] <- 0000c6c8(b)<__gic_v3_set_lr+0x108>
~ │ │ │ │ │ │ │ │ 0000c6d0: f9002be8 str x8, [sp, #80]
~ │ │ │ │ │ │ │ │ 0000c6d4: f9402be8 ldr x8, [sp, #80]
~ │ │ │ │ │ │ │ │ 0000c6d8: d51ccce8 msr s3_4_c12_c12_7, x8
~ │ │ │ │ │ │ │ │ ┌─0000c6dc: 14000001 b c6e0 <__gic_v3_set_lr+0x11c>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc6cc 0xc6e0 (DW_OP_fbreg 0x50) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:86
│ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ __gic_v3_set_lr:87.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ │ ┌─────────────────└>0000c6e0: 14000039 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c6dc(b)<__gic_v3_set_lr+0x11c>
│ │ │ │ │ │ │ │ │ __gic_v3_set_lr:89.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR8_EL2);
~ │ │ │ │ │ │ │ │ │ ┌─0000c6e4: 14000001 b c6e8 <__gic_v3_set_lr+0x124>
│ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:89.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR8_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc6e8 0xc6fc (DW_OP_fbreg 0x48) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:89
~ │ │ │ │ │ │ │ │ │ └>0000c6e8: f9404fe8 ldr x8, [sp, #152] <- 0000c6e4(b)<__gic_v3_set_lr+0x124>
~ │ │ │ │ │ │ │ │ │ 0000c6ec: f90027e8 str x8, [sp, #72]
~ │ │ │ │ │ │ │ │ │ 0000c6f0: f94027e8 ldr x8, [sp, #72]
~ │ │ │ │ │ │ │ │ │ 0000c6f4: d51ccd08 msr s3_4_c12_c13_0, x8
~ │ │ │ │ │ │ │ │ │ ┌─0000c6f8: 14000001 b c6fc <__gic_v3_set_lr+0x138>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc6e8 0xc6fc (DW_OP_fbreg 0x48) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:89
│ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:90.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ │ │ ┌───────────────└>0000c6fc: 14000032 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c6f8(b)<__gic_v3_set_lr+0x138>
│ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:92.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR9_EL2);
~ │ │ │ │ │ │ │ │ │ │ ┌─0000c700: 14000001 b c704 <__gic_v3_set_lr+0x140>
│ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:92.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR9_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc704 0xc718 (DW_OP_fbreg 0x40) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:92
~ │ │ │ │ │ │ │ │ │ │ └>0000c704: f9404fe8 ldr x8, [sp, #152] <- 0000c700(b)<__gic_v3_set_lr+0x140>
~ │ │ │ │ │ │ │ │ │ │ 0000c708: f90023e8 str x8, [sp, #64]
~ │ │ │ │ │ │ │ │ │ │ 0000c70c: f94023e8 ldr x8, [sp, #64]
~ │ │ │ │ │ │ │ │ │ │ 0000c710: d51ccd28 msr s3_4_c12_c13_1, x8
~ │ │ │ │ │ │ │ │ │ │ ┌─0000c714: 14000001 b c718 <__gic_v3_set_lr+0x154>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc704 0xc718 (DW_OP_fbreg 0x40) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:92
│ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:93.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ │ │ │ ┌─────────────└>0000c718: 1400002b b c7c4 <__gic_v3_set_lr+0x200> <- 0000c714(b)<__gic_v3_set_lr+0x154>
│ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:95.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR10_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c71c: 14000001 b c720 <__gic_v3_set_lr+0x15c>
│ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:95.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR10_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc720 0xc734 (DW_OP_fbreg 0x38) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:95
~ │ │ │ │ │ │ │ │ │ │ │ └>0000c720: f9404fe8 ldr x8, [sp, #152] <- 0000c71c(b)<__gic_v3_set_lr+0x15c>
~ │ │ │ │ │ │ │ │ │ │ │ 0000c724: f9001fe8 str x8, [sp, #56]
~ │ │ │ │ │ │ │ │ │ │ │ 0000c728: f9401fe8 ldr x8, [sp, #56]
~ │ │ │ │ │ │ │ │ │ │ │ 0000c72c: d51ccd48 msr s3_4_c12_c13_2, x8
~ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c730: 14000001 b c734 <__gic_v3_set_lr+0x170>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc720 0xc734 (DW_OP_fbreg 0x38) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:95
│ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:96.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ │ │ │ │ ┌───────────└>0000c734: 14000024 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c730(b)<__gic_v3_set_lr+0x170>
│ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:98.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR11_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c738: 14000001 b c73c <__gic_v3_set_lr+0x178>
│ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:98.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR11_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc73c 0xc750 (DW_OP_fbreg 0x30) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:98
~ │ │ │ │ │ │ │ │ │ │ │ │ └>0000c73c: f9404fe8 ldr x8, [sp, #152] <- 0000c738(b)<__gic_v3_set_lr+0x178>
~ │ │ │ │ │ │ │ │ │ │ │ │ 0000c740: f9001be8 str x8, [sp, #48]
~ │ │ │ │ │ │ │ │ │ │ │ │ 0000c744: f9401be8 ldr x8, [sp, #48]
~ │ │ │ │ │ │ │ │ │ │ │ │ 0000c748: d51ccd68 msr s3_4_c12_c13_3, x8
~ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c74c: 14000001 b c750 <__gic_v3_set_lr+0x18c>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc73c 0xc750 (DW_OP_fbreg 0x30) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:98
│ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:99.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ │ │ │ │ │ ┌─────────└>0000c750: 1400001d b c7c4 <__gic_v3_set_lr+0x200> <- 0000c74c(b)<__gic_v3_set_lr+0x18c>
│ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:101.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR12_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c754: 14000001 b c758 <__gic_v3_set_lr+0x194>
│ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:101.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR12_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc758 0xc76c (DW_OP_fbreg 0x28) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:101
~ │ │ │ │ │ │ │ │ │ │ │ │ │ └>0000c758: f9404fe8 ldr x8, [sp, #152] <- 0000c754(b)<__gic_v3_set_lr+0x194>
~ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c75c: f90017e8 str x8, [sp, #40]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c760: f94017e8 ldr x8, [sp, #40]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c764: d51ccd88 msr s3_4_c12_c13_4, x8
~ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c768: 14000001 b c76c <__gic_v3_set_lr+0x1a8>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc758 0xc76c (DW_OP_fbreg 0x28) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:101
│ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:102.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌───────└>0000c76c: 14000016 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c768(b)<__gic_v3_set_lr+0x1a8>
│ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:104.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR13_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c770: 14000001 b c774 <__gic_v3_set_lr+0x1b0>
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:104.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR13_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc774 0xc788 (DW_OP_fbreg 0x20) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:104
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ └>0000c774: f9404fe8 ldr x8, [sp, #152] <- 0000c770(b)<__gic_v3_set_lr+0x1b0>
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c778: f90013e8 str x8, [sp, #32]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c77c: f94013e8 ldr x8, [sp, #32]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c780: d51ccda8 msr s3_4_c12_c13_5, x8
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c784: 14000001 b c788 <__gic_v3_set_lr+0x1c4>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc774 0xc788 (DW_OP_fbreg 0x20) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:104
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:105.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─────└>0000c788: 1400000f b c7c4 <__gic_v3_set_lr+0x200> <- 0000c784(b)<__gic_v3_set_lr+0x1c4>
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:107.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR14_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c78c: 14000001 b c790 <__gic_v3_set_lr+0x1cc>
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:107.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR14_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc790 0xc7a4 (DW_OP_fbreg 0x18) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:107
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ └>0000c790: f9404fe8 ldr x8, [sp, #152] <- 0000c78c(b)<__gic_v3_set_lr+0x1cc>
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c794: f9000fe8 str x8, [sp, #24]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c798: f9400fe8 ldr x8, [sp, #24]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c79c: d51ccdc8 msr s3_4_c12_c13_6, x8
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c7a0: 14000001 b c7a4 <__gic_v3_set_lr+0x1e0>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc790 0xc7a4 (DW_OP_fbreg 0x18) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:107
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:108.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌───└>0000c7a4: 14000008 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c7a0(b)<__gic_v3_set_lr+0x1e0>
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:110.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_LR15_EL2);
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c7a8: 14000001 b c7ac <__gic_v3_set_lr+0x1e8>
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:110.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_LR15_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc7ac 0xc7c0 (DW_OP_fbreg 0x10) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:110
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ └>0000c7ac: f9404fe8 ldr x8, [sp, #152] <- 0000c7a8(b)<__gic_v3_set_lr+0x1e8>
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c7b0: f9000be8 str x8, [sp, #16]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c7b4: f9400be8 ldr x8, [sp, #16]
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ 0000c7b8: d51ccde8 msr s3_4_c12_c13_7, x8
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─0000c7bc: 14000001 b c7c0 <__gic_v3_set_lr+0x1fc>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc7ac 0xc7c0 (DW_OP_fbreg 0x10) lexblock:__gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:110
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:111.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─└>0000c7c0: 14000001 b c7c4 <__gic_v3_set_lr+0x200> <- 0000c7bc(b)<__gic_v3_set_lr+0x1fc>
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ __gic_v3_set_lr:113.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>└>└>└>└>└>└>└>└>└>└>└>└>└>└>└──>0000c7c4: 910283ff add sp, sp, #0xa0 <- 0000c5e8(b.cc)<__gic_v3_set_lr+0x200>,0000c61c(b)<__gic_v3_set_lr+0x200>,0000c638(b)<__gic_v3_set_lr+0x200>,0000c654(b)<__gic_v3_set_lr+0x200>,0000c670(b)<__gic_v3_set_lr+0x200>,0000c68c(b)<__gic_v3_set_lr+0x200>,0000c6a8(b)<__gic_v3_set_lr+0x200>,0000c6c4(b)<__gic_v3_set_lr+0x200>,0000c6e0(b)<__gic_v3_set_lr+0x200>,0000c6fc(b)<__gic_v3_set_lr+0x200>,0000c718(b)<__gic_v3_set_lr+0x200>,0000c734(b)<__gic_v3_set_lr+0x200>,0000c750(b)<__gic_v3_set_lr+0x200>,0000c76c(b)<__gic_v3_set_lr+0x200>,0000c788(b)<__gic_v3_set_lr+0x200>,0000c7a4(b)<__gic_v3_set_lr+0x200>,0000c7c0(b)<__gic_v3_set_lr+0x200>
0000c5c8 CFA:r31+160
~ 0000c7c8: d65f03c0 ret
-val param typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc5c4 0xc7cc (DW_OP_fbreg 0x98) __gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:61
-lr param int (base type, DW_ATE_signed size:4) 0xc5c4 0xc7cc (DW_OP_fbreg 0x94) __gic_v3_set_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:61
**0000c7cc <__vgic_v3_restore_state>:
+ __vgic_v3_restore_state params:
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc7cc 0xc8c4 (DW_OP_fbreg -0x10)
__vgic_v3_restore_state:235.0 (vgic-v3-sr.c) Sbepe ║{
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc7cc 0xc8c4 (DW_OP_fbreg -0x10) __vgic_v3_restore_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:234
+used_lrs var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc7cc 0xc8c4 (DW_OP_breg31 0x18) __vgic_v3_restore_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:236
+i var int (base type, DW_ATE_signed size:4) 0xc7cc 0xc8c4 (DW_OP_breg31 0x14) __vgic_v3_restore_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:237
~ 0000c7cc: d10103ff sub sp, sp, #0x40 <- 00002cec(bl)<__vgic_v3_restore_state>
~ 0000c7d0: a9037bfd stp x29, x30, [sp, #48]
0000c7cc CFA:r31 r29:u r30:u
~ 0000c7d4: 9100c3fd add x29, sp, #0x30
~ 0000c7d8: f81f03a0 stur x0, [x29, #-16]
__vgic_v3_restore_state:236.17 (vgic-v3-sr.c) SbePe u64 used_lrs = ║cpu_if->used_lrs;
~ 0000c7dc: f85f03a8 ldur x8, [x29, #-16]
__vgic_v3_restore_state:236.25 (vgic-v3-sr.c) sbepe u64 used_lrs = cpu_if->║used_lrs;
~ 0000c7e0: b9413109 ldr w9, [x8, #304]
~ 0000c7e4: 2a0903e8 mov w8, w9
__vgic_v3_restore_state:236.6 (vgic-v3-sr.c) sbepe u64 ║used_lrs = cpu_if->used_lrs;
~ 0000c7e8: f9000fe8 str x8, [sp, #24]
__vgic_v3_restore_state:239.6 (vgic-v3-sr.c) Sbepe if (║used_lrs || cpu_if->its_vpe.its_vm) {
~ 0000c7ec: f9400fe8 ldr x8, [sp, #24]
__vgic_v3_restore_state:239.15 (vgic-v3-sr.c) sbepe if (used_lrs ║|| cpu_if->its_vpe.its_vm) {
~ ┌─────0000c7f0: b50000c8 cbnz x8, c808 <__vgic_v3_restore_state+0x3c>
│
~ │ ┌─0000c7f4: 14000001 b c7f8 <__vgic_v3_restore_state+0x2c> <- 0000c7f0(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_restore_state:239.18 (vgic-v3-sr.c) sbepe if (used_lrs || ║cpu_if->its_vpe.its_vm) {
~ │ └>0000c7f8: f85f03a8 ldur x8, [x29, #-16] <- 0000c7f4(b)<__vgic_v3_restore_state+0x2c>
│ __vgic_v3_restore_state:239.34 (vgic-v3-sr.c) sbepe if (used_lrs || cpu_if->its_vpe.║its_vm) {
~ │ 0000c7fc: f9405d08 ldr x8, [x8, #184]
│ __vgic_v3_restore_state:239.6 (vgic-v3-sr.c) sbepe if (║used_lrs || cpu_if->its_vpe.its_vm) {
~ ┌┼─────0000c800: b40003c8 cbz x8, c878 <__vgic_v3_restore_state+0xac>
││
~ ││ ┌─0000c804: 14000001 b c808 <__vgic_v3_restore_state+0x3c> <- 0000c800(b.cc-succ)<fallthrough>
││ │
││ │ __vgic_v3_restore_state:240.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
~ │└>┌─└>0000c808: 14000001 b c80c <__vgic_v3_restore_state+0x40> <- 0000c7f0(b.cc)<__vgic_v3_restore_state+0x3c>,0000c804(b)<__vgic_v3_restore_state+0x3c>
│ │
│ │ __vgic_v3_restore_state:240.3 (vgic-v3-sr.c) sbepe ║write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc80c 0xc828 (DW_OP_breg31 0x8) lexblock:__vgic_v3_restore_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:240
~ │ └──>0000c80c: f85f03a8 ldur x8, [x29, #-16] <- 0000c808(b)<__vgic_v3_restore_state+0x40>
~ │ 0000c810: b9400109 ldr w9, [x8]
~ │ 0000c814: 2a0903e8 mov w8, w9
~ │ 0000c818: f90007e8 str x8, [sp, #8]
~ │ 0000c81c: f94007e8 ldr x8, [sp, #8]
~ │ 0000c820: d51ccb08 msr s3_4_c12_c11_0, x8
~ │ ┌─0000c824: 14000001 b c828 <__vgic_v3_restore_state+0x5c>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc80c 0xc828 (DW_OP_breg31 0x8) lexblock:__vgic_v3_restore_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:240
│ │
~ │ └>0000c828: 2a1f03e8 mov w8, wzr <- 0000c824(b)<__vgic_v3_restore_state+0x5c>
│ __vgic_v3_restore_state:242.10 (vgic-v3-sr.c) Sbepe for (i ║= 0; i < used_lrs; i++)
~ │ 0000c82c: b90017e8 str w8, [sp, #20]
│ __vgic_v3_restore_state:242.8 (vgic-v3-sr.c) sbepe for (║i = 0; i < used_lrs; i++)
~ │ ┌─0000c830: 14000001 b c834 <__vgic_v3_restore_state+0x68>
│ │
│ │ __vgic_v3_restore_state:242.15 (vgic-v3-sr.c) sbepe for (i = 0; ║i < used_lrs; i++)
~ │ ╔═>└>0000c834: b98017e8 ldrsw x8, [sp, #20] <- 0000c830(b)<__vgic_v3_restore_state+0x68>,v0000c870(b)<__vgic_v3_restore_state+0x68>
│ ║ __vgic_v3_restore_state:242.19 (vgic-v3-sr.c) sbepe for (i = 0; i < ║used_lrs; i++)
~ │ ║ 0000c838: f9400fe9 ldr x9, [sp, #24]
│ ║ __vgic_v3_restore_state:242.3 (vgic-v3-sr.c) sbepe ║for (i = 0; i < used_lrs; i++)
~ │ ║ 0000c83c: eb090108 subs x8, x8, x9
~ │ ║┌───0000c840: 540001a2 b.cs c874 <__vgic_v3_restore_state+0xa8> // b.hs, b.nlast
│ ║│
~ │ ║│ ┌─0000c844: 14000001 b c848 <__vgic_v3_restore_state+0x7c> <- 0000c840(b.cc-succ)<fallthrough>
│ ║│ │
│ ║│ │ __vgic_v3_restore_state:243.20 (vgic-v3-sr.c) Sbepe __gic_v3_set_lr(║cpu_if->vgic_lr[i], i);
~ │ ║│ └>0000c848: f85f03a8 ldur x8, [x29, #-16] <- 0000c844(b)<__vgic_v3_restore_state+0x7c>
│ ║│ __vgic_v3_restore_state:243.36 (vgic-v3-sr.c) sbepe __gic_v3_set_lr(cpu_if->vgic_lr[║i], i);
~ │ ║│ 0000c84c: b98017e9 ldrsw x9, [sp, #20]
│ ║│ __vgic_v3_restore_state:243.28 (vgic-v3-sr.c) sbepe __gic_v3_set_lr(cpu_if->║vgic_lr[i], i);
~ │ ║│ 0000c850: 8b090d08 add x8, x8, x9, lsl #3
│ ║│ __vgic_v3_restore_state:243.20 (vgic-v3-sr.c) sbepe __gic_v3_set_lr(║cpu_if->vgic_lr[i], i);
~ │ ║│ 0000c854: f9401900 ldr x0, [x8, #48]
│ ║│ __vgic_v3_restore_state:243.4 (vgic-v3-sr.c) sbepe ║__gic_v3_set_lr(cpu_if->vgic_lr[i], i);
~ │ ║│ 0000c858: 2a0903e1 mov w1, w9
~ │ ║│ 0000c85c: 97ffff5a bl c5c4 <__gic_v3_set_lr>
│ ║│
~ │ ║│ ┌─0000c860: 14000001 b c864 <__vgic_v3_restore_state+0x98> <- 0000c85c(bl-succ)<return>
│ ║│ │
│ ║│ │ __vgic_v3_restore_state:242.30 (vgic-v3-sr.c) Sbepe for (i = 0; i < used_lrs; i║++)
~ │ ║│ └>0000c864: b94017e8 ldr w8, [sp, #20] <- 0000c860(b)<__vgic_v3_restore_state+0x98>
~ │ ║│ 0000c868: 11000508 add w8, w8, #0x1
~ │ ║│ 0000c86c: b90017e8 str w8, [sp, #20]
│ ║│ __vgic_v3_restore_state:242.3 (vgic-v3-sr.c) sbepe ║for (i = 0; i < used_lrs; i++)
~ │ ╚╪═══0000c870: 17fffff1 b c834 <__vgic_v3_restore_state+0x68>
│ │
│ │ __vgic_v3_restore_state:244.2 (vgic-v3-sr.c) Sbepe }
~ │ └>┌─0000c874: 14000001 b c878 <__vgic_v3_restore_state+0xac> <- 0000c840(b.cc)<__vgic_v3_restore_state+0xa8>
│ │
│ │ __vgic_v3_restore_state:252.6 (vgic-v3-sr.c) Sbepe if (║used_lrs || !has_vhe()) {
~ └───>└>0000c878: f9400fe8 ldr x8, [sp, #24] <- 0000c800(b.cc)<__vgic_v3_restore_state+0xac>,0000c874(b)<__vgic_v3_restore_state+0xac>
__vgic_v3_restore_state:252.15 (vgic-v3-sr.c) sbepe if (used_lrs ║|| !has_vhe()) {
~ ┌───0000c87c: b50000e8 cbnz x8, c898 <__vgic_v3_restore_state+0xcc>
│
~ │ ┌─0000c880: 14000001 b c884 <__vgic_v3_restore_state+0xb8> <- 0000c87c(b.cc-succ)<fallthrough>
│ │
~ │ └>0000c884: 2a1f03e8 mov w8, wzr <- 0000c880(b)<__vgic_v3_restore_state+0xb8>
d: 0xc888 0xc890 has_vhe inlined from __vgic_v3_restore_state:252 (vgic-v3-sr.c) <99c9e>:
d │ has_vhe:113.3 (virt.h) Sbepe ║return false;
~d │ 0000c888: 381ff3a8 sturb w8, [x29, #-1]
d │ has_vhe:116.1 (virt.h) Sbepe ║}
~d │ 0000c88c: 385ff3a8 ldurb w8, [x29, #-1]
│ __vgic_v3_restore_state:252.6 (vgic-v3-sr.c) Sbepe if (║used_lrs || !has_vhe()) {
~ ┌──┼───0000c890: 37000148 tbnz w8, #0, c8b8 <__vgic_v3_restore_state+0xec>
│ │
~ │ │ ┌─0000c894: 14000001 b c898 <__vgic_v3_restore_state+0xcc> <- 0000c890(b.cc-succ)<fallthrough>
│ │ │
│ │ │ __vgic_v3_restore_state:253.8 (vgic-v3-sr.c) Sbepe if (!║cpu_if->vgic_sre) {
~ │ └>└>0000c898: f85f03a8 ldur x8, [x29, #-16] <- 0000c87c(b.cc)<__vgic_v3_restore_state+0xcc>,0000c894(b)<__vgic_v3_restore_state+0xcc>
│ __vgic_v3_restore_state:253.16 (vgic-v3-sr.c) sbepe if (!cpu_if->║vgic_sre) {
~ │ 0000c89c: b9400909 ldr w9, [x8, #8]
│ __vgic_v3_restore_state:253.7 (vgic-v3-sr.c) sbepe if (║!cpu_if->vgic_sre) {
~ │┌─────0000c8a0: 350000a9 cbnz w9, c8b4 <__vgic_v3_restore_state+0xe8>
││
~ ││ ┌─0000c8a4: 14000001 b c8a8 <__vgic_v3_restore_state+0xdc> <- 0000c8a0(b.cc-succ)<fallthrough>
││ │
││ │ __vgic_v3_restore_state:254.4 (vgic-v3-sr.c) Sbepe ║isb();
~ ││ └>0000c8a8: d5033fdf isb <- 0000c8a4(b)<__vgic_v3_restore_state+0xdc>
││ __vgic_v3_restore_state:255.4 (vgic-v3-sr.c) Sbepe ║dsb(sy);
~ ││ 0000c8ac: d5033f9f dsb sy
││ __vgic_v3_restore_state:256.3 (vgic-v3-sr.c) Sbepe }
~ ││ ┌─0000c8b0: 14000001 b c8b4 <__vgic_v3_restore_state+0xe8>
││ │
││ │ __vgic_v3_restore_state:257.2 (vgic-v3-sr.c) Sbepe }
~ │└>┌─└>0000c8b4: 14000001 b c8b8 <__vgic_v3_restore_state+0xec> <- 0000c8a0(b.cc)<__vgic_v3_restore_state+0xe8>,0000c8b0(b)<__vgic_v3_restore_state+0xe8>
│ │
│ │ __vgic_v3_restore_state:258.1 (vgic-v3-sr.c) Sbepe ║}
~ └─>└──>0000c8b8: a9437bfd ldp x29, x30, [sp, #48] <- 0000c890(b.cc)<__vgic_v3_restore_state+0xec>,0000c8b4(b)<__vgic_v3_restore_state+0xec>
~ 0000c8bc: 910103ff add sp, sp, #0x40
0000c7d8 CFA:r29+16 r29:c-16 r30:c-8
~ 0000c8c0: d65f03c0 ret
-cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc7cc 0xc8c4 (DW_OP_fbreg -0x10) __vgic_v3_restore_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:234
-used_lrs var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc7cc 0xc8c4 (DW_OP_breg31 0x18) __vgic_v3_restore_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:236
-i var int (base type, DW_ATE_signed size:4) 0xc7cc 0xc8c4 (DW_OP_breg31 0x14) __vgic_v3_restore_state:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:237
**0000c8c4 <__vgic_v3_activate_traps>:
+ __vgic_v3_activate_traps params:
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc8c4 0xc9d8 (DW_OP_fbreg 0x40)
__vgic_v3_activate_traps:261.0 (vgic-v3-sr.c) Sbepe ║{
0000c8c4 CFA:r31
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc8c4 0xc9d8 (DW_OP_fbreg 0x40) __vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:260
~ 0000c8c4: d10143ff sub sp, sp, #0x50 <- 00002ce0(bl)<__vgic_v3_activate_traps>
~ 0000c8c8: f90023e0 str x0, [sp, #64]
__vgic_v3_activate_traps:272.7 (vgic-v3-sr.c) SbePe if (!║cpu_if->vgic_sre) {
~ 0000c8cc: f94023e8 ldr x8, [sp, #64]
__vgic_v3_activate_traps:272.15 (vgic-v3-sr.c) sbepe if (!cpu_if->║vgic_sre) {
~ 0000c8d0: b9400909 ldr w9, [x8, #8]
__vgic_v3_activate_traps:272.6 (vgic-v3-sr.c) sbepe if (║!cpu_if->vgic_sre) {
~ ┌───────0000c8d4: 35000369 cbnz w9, c940 <__vgic_v3_activate_traps+0x7c>
│
~ │ ┌─0000c8d8: 14000001 b c8dc <__vgic_v3_activate_traps+0x18> <- 0000c8d4(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_activate_traps:273.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(0, ICC_SRE_EL1);
~ │ ┌─└>0000c8dc: 14000001 b c8e0 <__vgic_v3_activate_traps+0x1c> <- 0000c8d8(b)<__vgic_v3_activate_traps+0x18>
│ │
~ │ └──>0000c8e0: aa1f03e8 mov x8, xzr <- 0000c8dc(b)<__vgic_v3_activate_traps+0x1c>
│ __vgic_v3_activate_traps:273.3 (vgic-v3-sr.c) sbepe ║write_gicreg(0, ICC_SRE_EL1);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc8e4 0xc8f4 (DW_OP_fbreg 0x38) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:273
~ │ 0000c8e4: f9001fe8 str x8, [sp, #56]
~ │ 0000c8e8: f9401fe8 ldr x8, [sp, #56]
~ │ 0000c8ec: d518cca8 msr s3_0_c12_c12_5, x8
~ │ ┌─0000c8f0: 14000001 b c8f4 <__vgic_v3_activate_traps+0x30>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc8e4 0xc8f4 (DW_OP_fbreg 0x38) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:273
│ │
│ │ __vgic_v3_activate_traps:274.3 (vgic-v3-sr.c) Sbepe ║isb();
~ │ └>0000c8f4: d5033fdf isb <- 0000c8f0(b)<__vgic_v3_activate_traps+0x30>
│ __vgic_v3_activate_traps:275.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
~ │ ┌─0000c8f8: 14000001 b c8fc <__vgic_v3_activate_traps+0x38>
│ │
│ │ __vgic_v3_activate_traps:275.3 (vgic-v3-sr.c) sbepe ║write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc8fc 0xc918 (DW_OP_fbreg 0x30) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:275
~ │ └>0000c8fc: f94023e8 ldr x8, [sp, #64] <- 0000c8f8(b)<__vgic_v3_activate_traps+0x38>
~ │ 0000c900: b9400509 ldr w9, [x8, #4]
~ │ 0000c904: 2a0903e8 mov w8, w9
~ │ 0000c908: f9001be8 str x8, [sp, #48]
~ │ 0000c90c: f9401be8 ldr x8, [sp, #48]
~ │ 0000c910: d51ccbe8 msr s3_4_c12_c11_7, x8
~ │ ┌─0000c914: 14000001 b c918 <__vgic_v3_activate_traps+0x54>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc8fc 0xc918 (DW_OP_fbreg 0x30) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:275
│ │
~ │ └>0000c918: 2a1f03e8 mov w8, wzr <- 0000c914(b)<__vgic_v3_activate_traps+0x54>
e: 0xc91c 0xc924 has_vhe inlined from __vgic_v3_activate_traps:278 (vgic-v3-sr.c) <99d13>:
e │ has_vhe:113.3 (virt.h) Sbepe ║return false;
~e │ 0000c91c: 39013fe8 strb w8, [sp, #79]
e │ has_vhe:116.1 (virt.h) Sbepe ║}
~e │ 0000c920: 39413fe8 ldrb w8, [sp, #79]
│ __vgic_v3_activate_traps:278.7 (vgic-v3-sr.c) Sbepe if (║has_vhe()) {
~ │ 0000c924: 71000508 subs w8, w8, #0x1
~ │ ┌─────0000c928: 540000a1 b.ne c93c <__vgic_v3_activate_traps+0x78> // b.any
│ │
~ │ │ ┌─0000c92c: 14000001 b c930 <__vgic_v3_activate_traps+0x6c> <- 0000c928(b.cc-succ)<fallthrough>
│ │ │
│ │ │ __vgic_v3_activate_traps:285.4 (vgic-v3-sr.c) Sbepe ║isb();
~ │ │ └>0000c930: d5033fdf isb <- 0000c92c(b)<__vgic_v3_activate_traps+0x6c>
│ │ __vgic_v3_activate_traps:286.4 (vgic-v3-sr.c) Sbepe ║dsb(sy);
~ │ │ 0000c934: d5033f9f dsb sy
│ │ __vgic_v3_activate_traps:287.3 (vgic-v3-sr.c) Sbepe }
~ │ │ ┌─0000c938: 14000001 b c93c <__vgic_v3_activate_traps+0x78>
│ │ │
│ │ │ __vgic_v3_activate_traps:288.2 (vgic-v3-sr.c) Sbepe }
~ │ └>┌─└>0000c93c: 14000001 b c940 <__vgic_v3_activate_traps+0x7c> <- 0000c928(b.cc)<__vgic_v3_activate_traps+0x78>,0000c938(b)<__vgic_v3_activate_traps+0x78>
│ │
│ │ __vgic_v3_activate_traps:294.2 (vgic-v3-sr.c) Sbepe ║write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
~ └>┌─└──>0000c940: 14000001 b c944 <__vgic_v3_activate_traps+0x80> <- 0000c8d4(b.cc)<__vgic_v3_activate_traps+0x7c>,0000c93c(b)<__vgic_v3_activate_traps+0x7c>
│
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc944 0xc96c (DW_OP_fbreg 0x28) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:294
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc944 0xc958 (DW_OP_fbreg 0x20) lexblock:lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:294
~ └────>0000c944: d53cc9a8 mrs x8, s3_4_c12_c9_5 <- 0000c940(b)<__vgic_v3_activate_traps+0x80>
__vgic_v3_activate_traps:294.2 (vgic-v3-sr.c) sbepe ║write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
~ 0000c948: f90013e8 str x8, [sp, #32]
~ 0000c94c: f94013e8 ldr x8, [sp, #32]
~ 0000c950: f9000fe8 str x8, [sp, #24]
~ 0000c954: f9400fe8 ldr x8, [sp, #24]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc944 0xc958 (DW_OP_fbreg 0x20) lexblock:lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:294
__vgic_v3_activate_traps:294.2 (vgic-v3-sr.c) sbepe ║write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
~ 0000c958: 927cf908 and x8, x8, #0xfffffffffffffff7
~ 0000c95c: f90017e8 str x8, [sp, #40]
~ 0000c960: f94017e8 ldr x8, [sp, #40]
~ 0000c964: d51cc9a8 msr s3_4_c12_c9_5, x8
~ ┌─0000c968: 14000001 b c96c <__vgic_v3_activate_traps+0xa8>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc944 0xc96c (DW_OP_fbreg 0x28) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:294
│
│ __vgic_v3_activate_traps:302.6 (vgic-v3-sr.c) Sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
+branch var typedef(bool=_Bool (base type, DW_ATE_boolean size:1)) 0xc96c 0xc994 (DW_OP_fbreg 0x14) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:302
~ └>0000c96c: f0000068 adrp x8, 1b000 <hyp_memory+0x460> <- 0000c968(b)<__vgic_v3_activate_traps+0xa8>
~ 0000c970: b947b109 ldr w9, [x8, #1968]
~ 0000c974: 71000129 subs w9, w9, #0x0
~ 0000c978: 1a9f07ea cset w10, ne // ne = any
~ 0000c97c: 390053ea strb w10, [sp, #20]
__vgic_v3_activate_traps:302.6 (vgic-v3-sr.c) sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ 0000c980: 394053ea ldrb w10, [sp, #20]
~ 0000c984: 2a0a03e8 mov w8, w10
~ 0000c988: 92400108 and x8, x8, #0x1
__vgic_v3_activate_traps:302.6 (vgic-v3-sr.c) sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ 0000c98c: f90007e8 str x8, [sp, #8]
__vgic_v3_activate_traps:302.6 (vgic-v3-sr.c) sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ 0000c990: f94007e8 ldr x8, [sp, #8]
-branch var typedef(bool=_Bool (base type, DW_ATE_boolean size:1)) 0xc96c 0xc994 (DW_OP_fbreg 0x14) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:302
__vgic_v3_activate_traps:302.50 (vgic-v3-sr.c) sbepe if (static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ ┌─────0000c994: b50000c8 cbnz x8, c9ac <__vgic_v3_activate_traps+0xe8>
│
~ │ ┌─0000c998: 14000001 b c99c <__vgic_v3_activate_traps+0xd8> <- 0000c994(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_activate_traps:303.6 (vgic-v3-sr.c) Sbepe ║cpu_if->its_vpe.its_vm)
~ │ └>0000c99c: f94023e8 ldr x8, [sp, #64] <- 0000c998(b)<__vgic_v3_activate_traps+0xd8>
│ __vgic_v3_activate_traps:303.22 (vgic-v3-sr.c) sbepe cpu_if->its_vpe.║its_vm)
~ │ 0000c9a0: f9405d08 ldr x8, [x8, #184]
│ __vgic_v3_activate_traps:302.6 (vgic-v3-sr.c) Sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ ┌┼─────0000c9a4: b4000168 cbz x8, c9d0 <__vgic_v3_activate_traps+0x10c>
││
~ ││ ┌─0000c9a8: 14000001 b c9ac <__vgic_v3_activate_traps+0xe8> <- 0000c9a4(b.cc-succ)<fallthrough>
││ │
││ │ __vgic_v3_activate_traps:304.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
~ │└>┌─└>0000c9ac: 14000001 b c9b0 <__vgic_v3_activate_traps+0xec> <- 0000c994(b.cc)<__vgic_v3_activate_traps+0xe8>,0000c9a8(b)<__vgic_v3_activate_traps+0xe8>
│ │
│ │ __vgic_v3_activate_traps:304.3 (vgic-v3-sr.c) sbepe ║write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc9b0 0xc9d0 (DW_OP_fbreg 0x0) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:304
~ │ └──>0000c9b0: f94023e8 ldr x8, [sp, #64] <- 0000c9ac(b)<__vgic_v3_activate_traps+0xec>
~ │ 0000c9b4: b9400109 ldr w9, [x8]
~ │ 0000c9b8: 2a0903e8 mov w8, w9
~ │ 0000c9bc: f90003e8 str x8, [sp]
~ │ 0000c9c0: f94003e8 ldr x8, [sp]
~ │ 0000c9c4: d51ccb08 msr s3_4_c12_c11_0, x8
~ │ ┌─0000c9c8: 14000001 b c9cc <__vgic_v3_activate_traps+0x108>
│ │
~ │ ┌─└>0000c9cc: 14000001 b c9d0 <__vgic_v3_activate_traps+0x10c> <- 0000c9c8(b)<__vgic_v3_activate_traps+0x108>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc9b0 0xc9d0 (DW_OP_fbreg 0x0) lexblock:__vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:304
│ │
│ │ __vgic_v3_activate_traps:305.1 (vgic-v3-sr.c) Sbepe ║}
~ └─>└──>0000c9d0: 910143ff add sp, sp, #0x50 <- 0000c9a4(b.cc)<__vgic_v3_activate_traps+0x10c>,0000c9cc(b)<__vgic_v3_activate_traps+0x10c>
0000c8c8 CFA:r31+80
~ 0000c9d4: d65f03c0 ret
-cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc8c4 0xc9d8 (DW_OP_fbreg 0x40) __vgic_v3_activate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:260
**0000c9d8 <__vgic_v3_deactivate_traps>:
+ __vgic_v3_deactivate_traps params:
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc9d8 0xcadc (DW_OP_fbreg 0x58)
__vgic_v3_deactivate_traps:308.0 (vgic-v3-sr.c) Sbepe ║{
0000c9d8 CFA:r31
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc9d8 0xcadc (DW_OP_fbreg 0x58) __vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:307
+val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc9d8 0xcadc (DW_OP_fbreg 0x50) __vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:309
~ 0000c9d8: d10183ff sub sp, sp, #0x60 <- 0000337c(bl)<__vgic_v3_deactivate_traps>
~ 0000c9dc: f9002fe0 str x0, [sp, #88]
__vgic_v3_deactivate_traps:311.7 (vgic-v3-sr.c) SbePe if (!║cpu_if->vgic_sre) {
~ 0000c9e0: f9402fe8 ldr x8, [sp, #88]
__vgic_v3_deactivate_traps:311.15 (vgic-v3-sr.c) sbepe if (!cpu_if->║vgic_sre) {
~ 0000c9e4: b9400909 ldr w9, [x8, #8]
__vgic_v3_deactivate_traps:311.6 (vgic-v3-sr.c) sbepe if (║!cpu_if->vgic_sre) {
~ ┌───0000c9e8: 35000149 cbnz w9, ca10 <__vgic_v3_deactivate_traps+0x38>
│
~ │ ┌─0000c9ec: 14000001 b c9f0 <__vgic_v3_deactivate_traps+0x18> <- 0000c9e8(b.cc-succ)<fallthrough>
│ │
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc9f0 0xca04 (DW_OP_fbreg 0x48) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:312
~ │ └>0000c9f0: d53ccbe8 mrs x8, s3_4_c12_c11_7 <- 0000c9ec(b)<__vgic_v3_deactivate_traps+0x18>
│ __vgic_v3_deactivate_traps:312.23 (vgic-v3-sr.c) Sbepe cpu_if->vgic_vmcr = ║read_gicreg(ICH_VMCR_EL2);
~ │ 0000c9f4: f90027e8 str x8, [sp, #72]
~ │ 0000c9f8: f94027e8 ldr x8, [sp, #72]
~ │ 0000c9fc: f90023e8 str x8, [sp, #64]
~ │ 0000ca00: f94023e8 ldr x8, [sp, #64]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc9f0 0xca04 (DW_OP_fbreg 0x48) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:312
│ __vgic_v3_deactivate_traps:312.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);
~ │ 0000ca04: f9402fe9 ldr x9, [sp, #88]
│ __vgic_v3_deactivate_traps:312.21 (vgic-v3-sr.c) sbepe cpu_if->vgic_vmcr ║= read_gicreg(ICH_VMCR_EL2);
~ │ 0000ca08: b9000528 str w8, [x9, #4]
│ __vgic_v3_deactivate_traps:313.2 (vgic-v3-sr.c) Sbepe }
~ │ ┌─0000ca0c: 14000001 b ca10 <__vgic_v3_deactivate_traps+0x38>
│ │
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xca10 0xca24 (DW_OP_fbreg 0x38) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:315
~ └>└>0000ca10: d53cc9a8 mrs x8, s3_4_c12_c9_5 <- 0000c9e8(b.cc)<__vgic_v3_deactivate_traps+0x38>,0000ca0c(b)<__vgic_v3_deactivate_traps+0x38>
__vgic_v3_deactivate_traps:315.8 (vgic-v3-sr.c) Sbepe val = ║read_gicreg(ICC_SRE_EL2);
~ 0000ca14: f9001fe8 str x8, [sp, #56]
~ 0000ca18: f9401fe8 ldr x8, [sp, #56]
~ 0000ca1c: f9001be8 str x8, [sp, #48]
~ 0000ca20: f9401be8 ldr x8, [sp, #48]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xca10 0xca24 (DW_OP_fbreg 0x38) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:315
__vgic_v3_deactivate_traps:315.6 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICC_SRE_EL2);
~ 0000ca24: f9002be8 str x8, [sp, #80]
__vgic_v3_deactivate_traps:316.2 (vgic-v3-sr.c) Sbepe ║write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
~ ┌─0000ca28: 14000001 b ca2c <__vgic_v3_deactivate_traps+0x54>
│
│ __vgic_v3_deactivate_traps:316.2 (vgic-v3-sr.c) sbepe ║write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xca2c 0xca44 (DW_OP_fbreg 0x28) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:316
~ └>0000ca2c: f9402be8 ldr x8, [sp, #80] <- 0000ca28(b)<__vgic_v3_deactivate_traps+0x54>
~ 0000ca30: b27d0108 orr x8, x8, #0x8
~ 0000ca34: f90017e8 str x8, [sp, #40]
~ 0000ca38: f94017e8 ldr x8, [sp, #40]
~ 0000ca3c: d51cc9a8 msr s3_4_c12_c9_5, x8
~ ┌─0000ca40: 14000001 b ca44 <__vgic_v3_deactivate_traps+0x6c>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xca2c 0xca44 (DW_OP_fbreg 0x28) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:316
│
│ __vgic_v3_deactivate_traps:318.7 (vgic-v3-sr.c) Sbepe if (!║cpu_if->vgic_sre) {
~ └>0000ca44: f9402fe8 ldr x8, [sp, #88] <- 0000ca40(b)<__vgic_v3_deactivate_traps+0x6c>
__vgic_v3_deactivate_traps:318.15 (vgic-v3-sr.c) sbepe if (!cpu_if->║vgic_sre) {
~ 0000ca48: b9400909 ldr w9, [x8, #8]
__vgic_v3_deactivate_traps:318.6 (vgic-v3-sr.c) sbepe if (║!cpu_if->vgic_sre) {
~ ┌─────0000ca4c: 35000169 cbnz w9, ca78 <__vgic_v3_deactivate_traps+0xa0>
│
~ │ ┌─0000ca50: 14000001 b ca54 <__vgic_v3_deactivate_traps+0x7c> <- 0000ca4c(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_deactivate_traps:320.3 (vgic-v3-sr.c) Sbepe ║isb();
~ │ └>0000ca54: d5033fdf isb <- 0000ca50(b)<__vgic_v3_deactivate_traps+0x7c>
│ __vgic_v3_deactivate_traps:321.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(1, ICC_SRE_EL1);
~ │ ┌─0000ca58: 14000001 b ca5c <__vgic_v3_deactivate_traps+0x84>
│ │
~ │ └>0000ca5c: 52800028 mov w8, #0x1 // #1 <- 0000ca58(b)<__vgic_v3_deactivate_traps+0x84>
~ │ 0000ca60: 2a0803e9 mov w9, w8
│ __vgic_v3_deactivate_traps:321.3 (vgic-v3-sr.c) sbepe ║write_gicreg(1, ICC_SRE_EL1);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xca64 0xca74 (DW_OP_fbreg 0x20) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:321
~ │ 0000ca64: f90013e9 str x9, [sp, #32]
~ │ 0000ca68: f94013e9 ldr x9, [sp, #32]
~ │ 0000ca6c: d518cca9 msr s3_0_c12_c12_5, x9
~ │ ┌─0000ca70: 14000001 b ca74 <__vgic_v3_deactivate_traps+0x9c>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xca64 0xca74 (DW_OP_fbreg 0x20) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:321
│ │
│ │ __vgic_v3_deactivate_traps:322.2 (vgic-v3-sr.c) Sbepe }
~ │ ┌─└>0000ca74: 14000001 b ca78 <__vgic_v3_deactivate_traps+0xa0> <- 0000ca70(b)<__vgic_v3_deactivate_traps+0x9c>
│ │
│ │ __vgic_v3_deactivate_traps:328.6 (vgic-v3-sr.c) Sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
+branch var typedef(bool=_Bool (base type, DW_ATE_boolean size:1)) 0xca78 0xcaa0 (DW_OP_fbreg 0x1c) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:328
~ └>└──>0000ca78: f0000068 adrp x8, 1b000 <hyp_memory+0x460> <- 0000ca4c(b.cc)<__vgic_v3_deactivate_traps+0xa0>,0000ca74(b)<__vgic_v3_deactivate_traps+0xa0>
~ 0000ca7c: b947b109 ldr w9, [x8, #1968]
~ 0000ca80: 71000129 subs w9, w9, #0x0
~ 0000ca84: 1a9f07ea cset w10, ne // ne = any
~ 0000ca88: 390073ea strb w10, [sp, #28]
__vgic_v3_deactivate_traps:328.6 (vgic-v3-sr.c) sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ 0000ca8c: 394073ea ldrb w10, [sp, #28]
~ 0000ca90: 2a0a03e8 mov w8, w10
~ 0000ca94: 92400108 and x8, x8, #0x1
__vgic_v3_deactivate_traps:328.6 (vgic-v3-sr.c) sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ 0000ca98: f9000be8 str x8, [sp, #16]
__vgic_v3_deactivate_traps:328.6 (vgic-v3-sr.c) sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ 0000ca9c: f9400be8 ldr x8, [sp, #16]
-branch var typedef(bool=_Bool (base type, DW_ATE_boolean size:1)) 0xca78 0xcaa0 (DW_OP_fbreg 0x1c) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:328
__vgic_v3_deactivate_traps:328.50 (vgic-v3-sr.c) sbepe if (static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ ┌─────0000caa0: b50000c8 cbnz x8, cab8 <__vgic_v3_deactivate_traps+0xe0>
│
~ │ ┌─0000caa4: 14000001 b caa8 <__vgic_v3_deactivate_traps+0xd0> <- 0000caa0(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_deactivate_traps:329.6 (vgic-v3-sr.c) Sbepe ║cpu_if->its_vpe.its_vm)
~ │ └>0000caa8: f9402fe8 ldr x8, [sp, #88] <- 0000caa4(b)<__vgic_v3_deactivate_traps+0xd0>
│ __vgic_v3_deactivate_traps:329.22 (vgic-v3-sr.c) sbepe cpu_if->its_vpe.║its_vm)
~ │ 0000caac: f9405d08 ldr x8, [x8, #184]
│ __vgic_v3_deactivate_traps:328.6 (vgic-v3-sr.c) Sbepe if (║static_branch_unlikely(&vgic_v3_cpuif_trap) ||
~ ┌┼─────0000cab0: b4000128 cbz x8, cad4 <__vgic_v3_deactivate_traps+0xfc>
││
~ ││ ┌─0000cab4: 14000001 b cab8 <__vgic_v3_deactivate_traps+0xe0> <- 0000cab0(b.cc-succ)<fallthrough>
││ │
││ │ __vgic_v3_deactivate_traps:330.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(0, ICH_HCR_EL2);
~ │└>┌─└>0000cab8: 14000001 b cabc <__vgic_v3_deactivate_traps+0xe4> <- 0000caa0(b.cc)<__vgic_v3_deactivate_traps+0xe0>,0000cab4(b)<__vgic_v3_deactivate_traps+0xe0>
│ │
~ │ └──>0000cabc: aa1f03e8 mov x8, xzr <- 0000cab8(b)<__vgic_v3_deactivate_traps+0xe4>
│ __vgic_v3_deactivate_traps:330.3 (vgic-v3-sr.c) sbepe ║write_gicreg(0, ICH_HCR_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcac0 0xcad4 (DW_OP_fbreg 0x8) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:330
~ │ 0000cac0: f90007e8 str x8, [sp, #8]
~ │ 0000cac4: f94007e8 ldr x8, [sp, #8]
~ │ 0000cac8: d51ccb08 msr s3_4_c12_c11_0, x8
~ │ ┌─0000cacc: 14000001 b cad0 <__vgic_v3_deactivate_traps+0xf8>
│ │
~ │ ┌─└>0000cad0: 14000001 b cad4 <__vgic_v3_deactivate_traps+0xfc> <- 0000cacc(b)<__vgic_v3_deactivate_traps+0xf8>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcac0 0xcad4 (DW_OP_fbreg 0x8) lexblock:__vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:330
│ │
│ │ __vgic_v3_deactivate_traps:331.1 (vgic-v3-sr.c) Sbepe ║}
~ └─>└──>0000cad4: 910183ff add sp, sp, #0x60 <- 0000cab0(b.cc)<__vgic_v3_deactivate_traps+0xfc>,0000cad0(b)<__vgic_v3_deactivate_traps+0xfc>
0000c9dc CFA:r31+96
~ 0000cad8: d65f03c0 ret
-cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xc9d8 0xcadc (DW_OP_fbreg 0x58) __vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:307
-val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xc9d8 0xcadc (DW_OP_fbreg 0x50) __vgic_v3_deactivate_traps:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:309
**0000cadc <__vgic_v3_save_aprs>:
+ __vgic_v3_save_aprs params:
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xcadc 0xcc08 (DW_OP_fbreg -0x8)
__vgic_v3_save_aprs:334.0 (vgic-v3-sr.c) Sbepe ║{
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xcadc 0xcc08 (DW_OP_fbreg -0x8) __vgic_v3_save_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:333
+val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcadc 0xcc08 (DW_OP_fbreg -0x10) __vgic_v3_save_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:335
+nr_pre_bits var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcadc 0xcc08 (DW_OP_fbreg -0x14) __vgic_v3_save_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:336
~ 0000cadc: d10103ff sub sp, sp, #0x40 <- 000074f8(bl)<__vgic_v3_save_aprs>
~ 0000cae0: a9037bfd stp x29, x30, [sp, #48]
0000cadc CFA:r31 r29:u r30:u
~ 0000cae4: 9100c3fd add x29, sp, #0x30
~ 0000cae8: f81f83a0 stur x0, [x29, #-8]
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcaec 0xcb00 (DW_OP_breg31 0x10) lexblock:__vgic_v3_save_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:338
~ 0000caec: d53ccb28 mrs x8, s3_4_c12_c11_1
__vgic_v3_save_aprs:338.8 (vgic-v3-sr.c) SbePe val = ║read_gicreg(ICH_VTR_EL2);
~ 0000caf0: f9000be8 str x8, [sp, #16]
~ 0000caf4: f9400be8 ldr x8, [sp, #16]
~ 0000caf8: f90007e8 str x8, [sp, #8]
~ 0000cafc: f94007e8 ldr x8, [sp, #8]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcaec 0xcb00 (DW_OP_breg31 0x10) lexblock:__vgic_v3_save_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:338
__vgic_v3_save_aprs:338.6 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_VTR_EL2);
~ 0000cb00: f81f03a8 stur x8, [x29, #-16]
__vgic_v3_save_aprs:339.16 (vgic-v3-sr.c) Sbepe nr_pre_bits = ║vtr_to_nr_pre_bits(val);
~ 0000cb04: b85f03a9 ldur w9, [x29, #-16]
~ 0000cb08: 531a7129 ubfx w9, w9, #26, #3
~ 0000cb0c: 11000529 add w9, w9, #0x1
__vgic_v3_save_aprs:339.14 (vgic-v3-sr.c) sbepe nr_pre_bits ║= vtr_to_nr_pre_bits(val);
~ 0000cb10: b81ec3a9 stur w9, [x29, #-20]
__vgic_v3_save_aprs:341.10 (vgic-v3-sr.c) Sbepe switch (║nr_pre_bits) {
~ 0000cb14: b85ec3a9 ldur w9, [x29, #-20]
__vgic_v3_save_aprs:341.2 (vgic-v3-sr.c) sbepe ║switch (nr_pre_bits) {
~ 0000cb18: 2a0903ea mov w10, w9
~ 0000cb1c: 71001929 subs w9, w9, #0x6
~ 0000cb20: b90007ea str w10, [sp, #4]
~ ┌───0000cb24: 540001e0 b.eq cb60 <__vgic_v3_save_aprs+0x84> // b.none
│
~ │ ┌─0000cb28: 14000001 b cb2c <__vgic_v3_save_aprs+0x50> <- 0000cb24(b.cc-succ)<fallthrough>
│ │
~ │ └>0000cb2c: b94007e8 ldr w8, [sp, #4] <- 0000cb28(b)<__vgic_v3_save_aprs+0x50>
│ __vgic_v3_save_aprs:341.2 (vgic-v3-sr.c) sbepe ║switch (nr_pre_bits) {
~ │ 0000cb30: 71001d09 subs w9, w8, #0x7
~ ┌┼───0000cb34: 54000201 b.ne cb74 <__vgic_v3_save_aprs+0x98> // b.any
││
~ ││ ┌─0000cb38: 14000001 b cb3c <__vgic_v3_save_aprs+0x60> <- 0000cb34(b.cc-succ)<fallthrough>
││ │
~ ││ └>0000cb3c: 52800060 mov w0, #0x3 // #3 <- 0000cb38(b)<__vgic_v3_save_aprs+0x60>
││ __vgic_v3_save_aprs:343.26 (vgic-v3-sr.c) Sbepe cpu_if->vgic_ap0r[3] = ║__vgic_v3_read_ap0rn(3);
~ ││ 0000cb40: 94000032 bl cc08 <__vgic_v3_read_ap0rn>
││
││ __vgic_v3_save_aprs:343.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap0r[3] = __vgic_v3_read_ap0rn(3);
~ ││ 0000cb44: f85f83a8 ldur x8, [x29, #-8] <- 0000cb40(bl-succ)<return>
││ __vgic_v3_save_aprs:343.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_ap0r[3] ║= __vgic_v3_read_ap0rn(3);
~ ││ 0000cb48: b9001900 str w0, [x8, #24]
~ ││ 0000cb4c: 52800040 mov w0, #0x2 // #2
││ __vgic_v3_save_aprs:344.26 (vgic-v3-sr.c) Sbepe cpu_if->vgic_ap0r[2] = ║__vgic_v3_read_ap0rn(2);
~ ││ 0000cb50: 9400002e bl cc08 <__vgic_v3_read_ap0rn>
││
││ __vgic_v3_save_aprs:344.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap0r[2] = __vgic_v3_read_ap0rn(2);
~ ││ 0000cb54: f85f83a8 ldur x8, [x29, #-8] <- 0000cb50(bl-succ)<return>
││ __vgic_v3_save_aprs:344.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_ap0r[2] ║= __vgic_v3_read_ap0rn(2);
~ ││ 0000cb58: b9001500 str w0, [x8, #20]
││ __vgic_v3_save_aprs:344.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap0r[2] = __vgic_v3_read_ap0rn(2);
~ ││ ┌─0000cb5c: 14000001 b cb60 <__vgic_v3_save_aprs+0x84>
││ │
~ │└>└>0000cb60: 52800020 mov w0, #0x1 // #1 <- 0000cb24(b.cc)<__vgic_v3_save_aprs+0x84>,0000cb5c(b)<__vgic_v3_save_aprs+0x84>
│ __vgic_v3_save_aprs:347.26 (vgic-v3-sr.c) Sbepe cpu_if->vgic_ap0r[1] = ║__vgic_v3_read_ap0rn(1);
~ │ 0000cb64: 94000029 bl cc08 <__vgic_v3_read_ap0rn>
│
│ __vgic_v3_save_aprs:347.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap0r[1] = __vgic_v3_read_ap0rn(1);
~ │ 0000cb68: f85f83a8 ldur x8, [x29, #-8] <- 0000cb64(bl-succ)<return>
│ __vgic_v3_save_aprs:347.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_ap0r[1] ║= __vgic_v3_read_ap0rn(1);
~ │ 0000cb6c: b9001100 str w0, [x8, #16]
│ __vgic_v3_save_aprs:347.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap0r[1] = __vgic_v3_read_ap0rn(1);
~ │ ┌─0000cb70: 14000001 b cb74 <__vgic_v3_save_aprs+0x98>
│ │
~ └─>└>0000cb74: 2a1f03e0 mov w0, wzr <- 0000cb34(b.cc)<__vgic_v3_save_aprs+0x98>,0000cb70(b)<__vgic_v3_save_aprs+0x98>
__vgic_v3_save_aprs:350.26 (vgic-v3-sr.c) Sbepe cpu_if->vgic_ap0r[0] = ║__vgic_v3_read_ap0rn(0);
~ 0000cb78: 94000024 bl cc08 <__vgic_v3_read_ap0rn>
__vgic_v3_save_aprs:350.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap0r[0] = __vgic_v3_read_ap0rn(0);
~ 0000cb7c: f85f83a8 ldur x8, [x29, #-8] <- 0000cb78(bl-succ)<return>
__vgic_v3_save_aprs:350.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_ap0r[0] ║= __vgic_v3_read_ap0rn(0);
~ 0000cb80: b9000d00 str w0, [x8, #12]
__vgic_v3_save_aprs:351.2 (vgic-v3-sr.c) Sbepe }
~ ┌─0000cb84: 14000001 b cb88 <__vgic_v3_save_aprs+0xac>
│
│ __vgic_v3_save_aprs:353.10 (vgic-v3-sr.c) Sbepe switch (║nr_pre_bits) {
~ └>0000cb88: b85ec3a8 ldur w8, [x29, #-20] <- 0000cb84(b)<__vgic_v3_save_aprs+0xac>
__vgic_v3_save_aprs:353.2 (vgic-v3-sr.c) sbepe ║switch (nr_pre_bits) {
~ 0000cb8c: 2a0803e9 mov w9, w8
~ 0000cb90: 71001908 subs w8, w8, #0x6
~ 0000cb94: b90003e9 str w9, [sp]
~ ┌───0000cb98: 540001e0 b.eq cbd4 <__vgic_v3_save_aprs+0xf8> // b.none
│
~ │ ┌─0000cb9c: 14000001 b cba0 <__vgic_v3_save_aprs+0xc4> <- 0000cb98(b.cc-succ)<fallthrough>
│ │
~ │ └>0000cba0: b94003e8 ldr w8, [sp] <- 0000cb9c(b)<__vgic_v3_save_aprs+0xc4>
│ __vgic_v3_save_aprs:353.2 (vgic-v3-sr.c) sbepe ║switch (nr_pre_bits) {
~ │ 0000cba4: 71001d09 subs w9, w8, #0x7
~ ┌┼───0000cba8: 54000201 b.ne cbe8 <__vgic_v3_save_aprs+0x10c> // b.any
││
~ ││ ┌─0000cbac: 14000001 b cbb0 <__vgic_v3_save_aprs+0xd4> <- 0000cba8(b.cc-succ)<fallthrough>
││ │
~ ││ └>0000cbb0: 52800060 mov w0, #0x3 // #3 <- 0000cbac(b)<__vgic_v3_save_aprs+0xd4>
││ __vgic_v3_save_aprs:355.26 (vgic-v3-sr.c) Sbepe cpu_if->vgic_ap1r[3] = ║__vgic_v3_read_ap1rn(3);
~ ││ 0000cbb4: 94000043 bl ccc0 <__vgic_v3_read_ap1rn>
││
││ __vgic_v3_save_aprs:355.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap1r[3] = __vgic_v3_read_ap1rn(3);
~ ││ 0000cbb8: f85f83a8 ldur x8, [x29, #-8] <- 0000cbb4(bl-succ)<return>
││ __vgic_v3_save_aprs:355.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_ap1r[3] ║= __vgic_v3_read_ap1rn(3);
~ ││ 0000cbbc: b9002900 str w0, [x8, #40]
~ ││ 0000cbc0: 52800040 mov w0, #0x2 // #2
││ __vgic_v3_save_aprs:356.26 (vgic-v3-sr.c) Sbepe cpu_if->vgic_ap1r[2] = ║__vgic_v3_read_ap1rn(2);
~ ││ 0000cbc4: 9400003f bl ccc0 <__vgic_v3_read_ap1rn>
││
││ __vgic_v3_save_aprs:356.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap1r[2] = __vgic_v3_read_ap1rn(2);
~ ││ 0000cbc8: f85f83a8 ldur x8, [x29, #-8] <- 0000cbc4(bl-succ)<return>
││ __vgic_v3_save_aprs:356.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_ap1r[2] ║= __vgic_v3_read_ap1rn(2);
~ ││ 0000cbcc: b9002500 str w0, [x8, #36]
││ __vgic_v3_save_aprs:356.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap1r[2] = __vgic_v3_read_ap1rn(2);
~ ││ ┌─0000cbd0: 14000001 b cbd4 <__vgic_v3_save_aprs+0xf8>
││ │
~ │└>└>0000cbd4: 52800020 mov w0, #0x1 // #1 <- 0000cb98(b.cc)<__vgic_v3_save_aprs+0xf8>,0000cbd0(b)<__vgic_v3_save_aprs+0xf8>
│ __vgic_v3_save_aprs:359.26 (vgic-v3-sr.c) Sbepe cpu_if->vgic_ap1r[1] = ║__vgic_v3_read_ap1rn(1);
~ │ 0000cbd8: 9400003a bl ccc0 <__vgic_v3_read_ap1rn>
│
│ __vgic_v3_save_aprs:359.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap1r[1] = __vgic_v3_read_ap1rn(1);
~ │ 0000cbdc: f85f83a8 ldur x8, [x29, #-8] <- 0000cbd8(bl-succ)<return>
│ __vgic_v3_save_aprs:359.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_ap1r[1] ║= __vgic_v3_read_ap1rn(1);
~ │ 0000cbe0: b9002100 str w0, [x8, #32]
│ __vgic_v3_save_aprs:359.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap1r[1] = __vgic_v3_read_ap1rn(1);
~ │ ┌─0000cbe4: 14000001 b cbe8 <__vgic_v3_save_aprs+0x10c>
│ │
~ └─>└>0000cbe8: 2a1f03e0 mov w0, wzr <- 0000cba8(b.cc)<__vgic_v3_save_aprs+0x10c>,0000cbe4(b)<__vgic_v3_save_aprs+0x10c>
__vgic_v3_save_aprs:362.26 (vgic-v3-sr.c) Sbepe cpu_if->vgic_ap1r[0] = ║__vgic_v3_read_ap1rn(0);
~ 0000cbec: 94000035 bl ccc0 <__vgic_v3_read_ap1rn>
__vgic_v3_save_aprs:362.3 (vgic-v3-sr.c) sbepe ║cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0);
~ 0000cbf0: f85f83a8 ldur x8, [x29, #-8] <- 0000cbec(bl-succ)<return>
__vgic_v3_save_aprs:362.24 (vgic-v3-sr.c) sbepe cpu_if->vgic_ap1r[0] ║= __vgic_v3_read_ap1rn(0);
~ 0000cbf4: b9001d00 str w0, [x8, #28]
__vgic_v3_save_aprs:363.2 (vgic-v3-sr.c) Sbepe }
~ ┌─0000cbf8: 14000001 b cbfc <__vgic_v3_save_aprs+0x120>
│
│ __vgic_v3_save_aprs:364.1 (vgic-v3-sr.c) Sbepe ║}
~ └>0000cbfc: a9437bfd ldp x29, x30, [sp, #48] <- 0000cbf8(b)<__vgic_v3_save_aprs+0x120>
~ 0000cc00: 910103ff add sp, sp, #0x40
0000cae8 CFA:r29+16 r29:c-16 r30:c-8
~ 0000cc04: d65f03c0 ret
-cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xcadc 0xcc08 (DW_OP_fbreg -0x8) __vgic_v3_save_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:333
-val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcadc 0xcc08 (DW_OP_fbreg -0x10) __vgic_v3_save_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:335
-nr_pre_bits var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcadc 0xcc08 (DW_OP_fbreg -0x14) __vgic_v3_save_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:336
**0000cc08 <__vgic_v3_read_ap0rn>:
+ __vgic_v3_read_ap0rn params:
+n param int (base type, DW_ATE_signed size:4) 0xcc08 0xccc0 (DW_OP_fbreg 0x4c)
__vgic_v3_read_ap0rn:152.0 (vgic-v3-sr.c) Sbepe ║{
0000cc08 CFA:r31
+n param int (base type, DW_ATE_signed size:4) 0xcc08 0xccc0 (DW_OP_fbreg 0x4c) __vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:151
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcc08 0xccc0 (DW_OP_fbreg 0x48) __vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:153
~ 0000cc08: d10143ff sub sp, sp, #0x50 <- 0000cb40(bl)<__vgic_v3_read_ap0rn>,0000cb50(bl)<__vgic_v3_read_ap0rn>,0000cb64(bl)<__vgic_v3_read_ap0rn>,0000cb78(bl)<__vgic_v3_read_ap0rn>,0000e92c(bl)<__vgic_v3_read_ap0rn>,0000eaa0(bl)<__vgic_v3_read_ap0rn>,0000ec08(bl)<__vgic_v3_read_ap0rn>,0000ef6c(bl)<__vgic_v3_read_ap0rn>
~ 0000cc0c: b9004fe0 str w0, [sp, #76]
__vgic_v3_read_ap0rn:155.10 (vgic-v3-sr.c) SbePe switch (║n) {
~ 0000cc10: b9404fe8 ldr w8, [sp, #76]
~ 0000cc14: 2a0803e9 mov w9, w8
~ 0000cc18: 2a0903e8 mov w8, w9
__vgic_v3_read_ap0rn:155.2 (vgic-v3-sr.c) sbepe ║switch (n) {
~ 0000cc1c: 71000d08 subs w8, w8, #0x3
~ 0000cc20: f90003e9 str x9, [sp]
~ ┌────0000cc24: 54000468 b.hi ccb0 <__vgic_v3_read_ap0rn+0xa8> // b.pmore
│
~ │ 0000cc28: f0000048 adrp x8, 17000 <___kvm_hyp_init+0x3c> <- 0000cc24(b.cc-succ)<fallthrough>
~ │ 0000cc2c: 913d3108 add x8, x8, #0xf4c
~ │ 0000cc30: f94003eb ldr x11, [sp]
~ │ 0000cc34: b8ab790a ldrsw x10, [x8, x11, lsl #2]
~ │ 0000cc38: 8b0a0109 add x9, x8, x10
│
~ │ X0000cc3c: d61f0120 br x9 -> 0000cc3c<indirect0> <- 0000cc3c(br)<indirect0>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcc40 0xcc54 (DW_OP_fbreg 0x40) lexblock:__vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:157
~ │ 0000cc40: d53cc808 mrs x8, s3_4_c12_c8_0
│ __vgic_v3_read_ap0rn:157.9 (vgic-v3-sr.c) Sbepe val = ║read_gicreg(ICH_AP0R0_EL2);
~ │ 0000cc44: f90023e8 str x8, [sp, #64]
~ │ 0000cc48: f94023e8 ldr x8, [sp, #64]
~ │ 0000cc4c: f9001fe8 str x8, [sp, #56]
~ │ 0000cc50: f9401fe8 ldr x8, [sp, #56]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcc40 0xcc54 (DW_OP_fbreg 0x40) lexblock:__vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:157
│ __vgic_v3_read_ap0rn:157.7 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_AP0R0_EL2);
~ │ 0000cc54: b9004be8 str w8, [sp, #72]
│ __vgic_v3_read_ap0rn:158.3 (vgic-v3-sr.c) Sbepe ║break;
~ ┌────┼────0000cc58: 14000017 b ccb4 <__vgic_v3_read_ap0rn+0xac>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcc5c 0xcc70 (DW_OP_fbreg 0x30) lexblock:__vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:160
~ │ │ 0000cc5c: d53cc828 mrs x8, s3_4_c12_c8_1
│ │ __vgic_v3_read_ap0rn:160.9 (vgic-v3-sr.c) Sbepe val = ║read_gicreg(ICH_AP0R1_EL2);
~ │ │ 0000cc60: f9001be8 str x8, [sp, #48]
~ │ │ 0000cc64: f9401be8 ldr x8, [sp, #48]
~ │ │ 0000cc68: f90017e8 str x8, [sp, #40]
~ │ │ 0000cc6c: f94017e8 ldr x8, [sp, #40]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcc5c 0xcc70 (DW_OP_fbreg 0x30) lexblock:__vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:160
│ │ __vgic_v3_read_ap0rn:160.7 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_AP0R1_EL2);
~ │ │ 0000cc70: b9004be8 str w8, [sp, #72]
│ │ __vgic_v3_read_ap0rn:161.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ ┌──┼────0000cc74: 14000010 b ccb4 <__vgic_v3_read_ap0rn+0xac>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcc78 0xcc8c (DW_OP_fbreg 0x20) lexblock:__vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:163
~ │ │ │ 0000cc78: d53cc848 mrs x8, s3_4_c12_c8_2
│ │ │ __vgic_v3_read_ap0rn:163.9 (vgic-v3-sr.c) Sbepe val = ║read_gicreg(ICH_AP0R2_EL2);
~ │ │ │ 0000cc7c: f90013e8 str x8, [sp, #32]
~ │ │ │ 0000cc80: f94013e8 ldr x8, [sp, #32]
~ │ │ │ 0000cc84: f9000fe8 str x8, [sp, #24]
~ │ │ │ 0000cc88: f9400fe8 ldr x8, [sp, #24]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcc78 0xcc8c (DW_OP_fbreg 0x20) lexblock:__vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:163
│ │ │ __vgic_v3_read_ap0rn:163.7 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_AP0R2_EL2);
~ │ │ │ 0000cc8c: b9004be8 str w8, [sp, #72]
│ │ │ __vgic_v3_read_ap0rn:164.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ┌┼────0000cc90: 14000009 b ccb4 <__vgic_v3_read_ap0rn+0xac>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcc94 0xcca8 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:166
~ │ │ ││ 0000cc94: d53cc868 mrs x8, s3_4_c12_c8_3
│ │ ││ __vgic_v3_read_ap0rn:166.9 (vgic-v3-sr.c) Sbepe val = ║read_gicreg(ICH_AP0R3_EL2);
~ │ │ ││ 0000cc98: f9000be8 str x8, [sp, #16]
~ │ │ ││ 0000cc9c: f9400be8 ldr x8, [sp, #16]
~ │ │ ││ 0000cca0: f90007e8 str x8, [sp, #8]
~ │ │ ││ 0000cca4: f94007e8 ldr x8, [sp, #8]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcc94 0xcca8 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:166
│ │ ││ __vgic_v3_read_ap0rn:166.7 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_AP0R3_EL2);
~ │ │ ││ 0000cca8: b9004be8 str w8, [sp, #72]
│ │ ││ __vgic_v3_read_ap0rn:167.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││┌───0000ccac: 14000002 b ccb4 <__vgic_v3_read_ap0rn+0xac>
│ │ │││
│ │ │││ __vgic_v3_read_ap0rn:169.3 (vgic-v3-sr.c) Sbepe ║unreachable();
~ │ │ │└┼>┌─0000ccb0: 14000001 b ccb4 <__vgic_v3_read_ap0rn+0xac> <- 0000cc24(b.cc)<__vgic_v3_read_ap0rn+0xa8>
│ │ │ │ │
│ │ │ │ │ __vgic_v3_read_ap0rn:172.9 (vgic-v3-sr.c) Sbepe return ║val;
~ └>└>└>└>└>0000ccb4: b9404be0 ldr w0, [sp, #72] <- 0000cc58(b)<__vgic_v3_read_ap0rn+0xac>,0000cc74(b)<__vgic_v3_read_ap0rn+0xac>,0000cc90(b)<__vgic_v3_read_ap0rn+0xac>,0000ccac(b)<__vgic_v3_read_ap0rn+0xac>,0000ccb0(b)<__vgic_v3_read_ap0rn+0xac>
__vgic_v3_read_ap0rn:172.2 (vgic-v3-sr.c) sbepe ║return val;
~ 0000ccb8: 910143ff add sp, sp, #0x50
0000cc0c CFA:r31+80
~ 0000ccbc: d65f03c0 ret
-n param int (base type, DW_ATE_signed size:4) 0xcc08 0xccc0 (DW_OP_fbreg 0x4c) __vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:151
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcc08 0xccc0 (DW_OP_fbreg 0x48) __vgic_v3_read_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:153
**0000ccc0 <__vgic_v3_read_ap1rn>:
+ __vgic_v3_read_ap1rn params:
+n param int (base type, DW_ATE_signed size:4) 0xccc0 0xcd78 (DW_OP_fbreg 0x4c)
__vgic_v3_read_ap1rn:176.0 (vgic-v3-sr.c) Sbepe ║{
0000ccc0 CFA:r31
+n param int (base type, DW_ATE_signed size:4) 0xccc0 0xcd78 (DW_OP_fbreg 0x4c) __vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:175
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xccc0 0xcd78 (DW_OP_fbreg 0x48) __vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:177
~ 0000ccc0: d10143ff sub sp, sp, #0x50 <- 0000cbb4(bl)<__vgic_v3_read_ap1rn>,0000cbc4(bl)<__vgic_v3_read_ap1rn>,0000cbd8(bl)<__vgic_v3_read_ap1rn>,0000cbec(bl)<__vgic_v3_read_ap1rn>,0000e938(bl)<__vgic_v3_read_ap1rn>,0000eacc(bl)<__vgic_v3_read_ap1rn>,0000ec14(bl)<__vgic_v3_read_ap1rn>,0000ef7c(bl)<__vgic_v3_read_ap1rn>
~ 0000ccc4: b9004fe0 str w0, [sp, #76]
__vgic_v3_read_ap1rn:179.10 (vgic-v3-sr.c) SbePe switch (║n) {
~ 0000ccc8: b9404fe8 ldr w8, [sp, #76]
~ 0000cccc: 2a0803e9 mov w9, w8
~ 0000ccd0: 2a0903e8 mov w8, w9
__vgic_v3_read_ap1rn:179.2 (vgic-v3-sr.c) sbepe ║switch (n) {
~ 0000ccd4: 71000d08 subs w8, w8, #0x3
~ 0000ccd8: f90003e9 str x9, [sp]
~ ┌────0000ccdc: 54000468 b.hi cd68 <__vgic_v3_read_ap1rn+0xa8> // b.pmore
│
~ │ 0000cce0: f0000048 adrp x8, 17000 <___kvm_hyp_init+0x3c> <- 0000ccdc(b.cc-succ)<fallthrough>
~ │ 0000cce4: 913d7108 add x8, x8, #0xf5c
~ │ 0000cce8: f94003eb ldr x11, [sp]
~ │ 0000ccec: b8ab790a ldrsw x10, [x8, x11, lsl #2]
~ │ 0000ccf0: 8b0a0109 add x9, x8, x10
│
~ │ X0000ccf4: d61f0120 br x9 -> 0000ccf4<indirect0> <- 0000ccf4(br)<indirect0>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xccf8 0xcd0c (DW_OP_fbreg 0x40) lexblock:__vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:181
~ │ 0000ccf8: d53cc908 mrs x8, s3_4_c12_c9_0
│ __vgic_v3_read_ap1rn:181.9 (vgic-v3-sr.c) Sbepe val = ║read_gicreg(ICH_AP1R0_EL2);
~ │ 0000ccfc: f90023e8 str x8, [sp, #64]
~ │ 0000cd00: f94023e8 ldr x8, [sp, #64]
~ │ 0000cd04: f9001fe8 str x8, [sp, #56]
~ │ 0000cd08: f9401fe8 ldr x8, [sp, #56]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xccf8 0xcd0c (DW_OP_fbreg 0x40) lexblock:__vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:181
│ __vgic_v3_read_ap1rn:181.7 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_AP1R0_EL2);
~ │ 0000cd0c: b9004be8 str w8, [sp, #72]
│ __vgic_v3_read_ap1rn:182.3 (vgic-v3-sr.c) Sbepe ║break;
~ ┌────┼────0000cd10: 14000017 b cd6c <__vgic_v3_read_ap1rn+0xac>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd14 0xcd28 (DW_OP_fbreg 0x30) lexblock:__vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:184
~ │ │ 0000cd14: d53cc928 mrs x8, s3_4_c12_c9_1
│ │ __vgic_v3_read_ap1rn:184.9 (vgic-v3-sr.c) Sbepe val = ║read_gicreg(ICH_AP1R1_EL2);
~ │ │ 0000cd18: f9001be8 str x8, [sp, #48]
~ │ │ 0000cd1c: f9401be8 ldr x8, [sp, #48]
~ │ │ 0000cd20: f90017e8 str x8, [sp, #40]
~ │ │ 0000cd24: f94017e8 ldr x8, [sp, #40]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd14 0xcd28 (DW_OP_fbreg 0x30) lexblock:__vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:184
│ │ __vgic_v3_read_ap1rn:184.7 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_AP1R1_EL2);
~ │ │ 0000cd28: b9004be8 str w8, [sp, #72]
│ │ __vgic_v3_read_ap1rn:185.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ ┌──┼────0000cd2c: 14000010 b cd6c <__vgic_v3_read_ap1rn+0xac>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd30 0xcd44 (DW_OP_fbreg 0x20) lexblock:__vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:187
~ │ │ │ 0000cd30: d53cc948 mrs x8, s3_4_c12_c9_2
│ │ │ __vgic_v3_read_ap1rn:187.9 (vgic-v3-sr.c) Sbepe val = ║read_gicreg(ICH_AP1R2_EL2);
~ │ │ │ 0000cd34: f90013e8 str x8, [sp, #32]
~ │ │ │ 0000cd38: f94013e8 ldr x8, [sp, #32]
~ │ │ │ 0000cd3c: f9000fe8 str x8, [sp, #24]
~ │ │ │ 0000cd40: f9400fe8 ldr x8, [sp, #24]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd30 0xcd44 (DW_OP_fbreg 0x20) lexblock:__vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:187
│ │ │ __vgic_v3_read_ap1rn:187.7 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_AP1R2_EL2);
~ │ │ │ 0000cd44: b9004be8 str w8, [sp, #72]
│ │ │ __vgic_v3_read_ap1rn:188.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ┌┼────0000cd48: 14000009 b cd6c <__vgic_v3_read_ap1rn+0xac>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd4c 0xcd60 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:190
~ │ │ ││ 0000cd4c: d53cc968 mrs x8, s3_4_c12_c9_3
│ │ ││ __vgic_v3_read_ap1rn:190.9 (vgic-v3-sr.c) Sbepe val = ║read_gicreg(ICH_AP1R3_EL2);
~ │ │ ││ 0000cd50: f9000be8 str x8, [sp, #16]
~ │ │ ││ 0000cd54: f9400be8 ldr x8, [sp, #16]
~ │ │ ││ 0000cd58: f90007e8 str x8, [sp, #8]
~ │ │ ││ 0000cd5c: f94007e8 ldr x8, [sp, #8]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd4c 0xcd60 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:190
│ │ ││ __vgic_v3_read_ap1rn:190.7 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_AP1R3_EL2);
~ │ │ ││ 0000cd60: b9004be8 str w8, [sp, #72]
│ │ ││ __vgic_v3_read_ap1rn:191.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││┌───0000cd64: 14000002 b cd6c <__vgic_v3_read_ap1rn+0xac>
│ │ │││
│ │ │││ __vgic_v3_read_ap1rn:193.3 (vgic-v3-sr.c) Sbepe ║unreachable();
~ │ │ │└┼>┌─0000cd68: 14000001 b cd6c <__vgic_v3_read_ap1rn+0xac> <- 0000ccdc(b.cc)<__vgic_v3_read_ap1rn+0xa8>
│ │ │ │ │
│ │ │ │ │ __vgic_v3_read_ap1rn:196.9 (vgic-v3-sr.c) Sbepe return ║val;
~ └>└>└>└>└>0000cd6c: b9404be0 ldr w0, [sp, #72] <- 0000cd10(b)<__vgic_v3_read_ap1rn+0xac>,0000cd2c(b)<__vgic_v3_read_ap1rn+0xac>,0000cd48(b)<__vgic_v3_read_ap1rn+0xac>,0000cd64(b)<__vgic_v3_read_ap1rn+0xac>,0000cd68(b)<__vgic_v3_read_ap1rn+0xac>
__vgic_v3_read_ap1rn:196.2 (vgic-v3-sr.c) sbepe ║return val;
~ 0000cd70: 910143ff add sp, sp, #0x50
0000ccc4 CFA:r31+80
~ 0000cd74: d65f03c0 ret
-n param int (base type, DW_ATE_signed size:4) 0xccc0 0xcd78 (DW_OP_fbreg 0x4c) __vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:175
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xccc0 0xcd78 (DW_OP_fbreg 0x48) __vgic_v3_read_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:177
**0000cd78 <__vgic_v3_restore_aprs>:
+ __vgic_v3_restore_aprs params:
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xcd78 0xcea4 (DW_OP_fbreg -0x8)
__vgic_v3_restore_aprs:367.0 (vgic-v3-sr.c) Sbepe ║{
+cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xcd78 0xcea4 (DW_OP_fbreg -0x8) __vgic_v3_restore_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:366
+val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd78 0xcea4 (DW_OP_fbreg -0x10) __vgic_v3_restore_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:368
+nr_pre_bits var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcd78 0xcea4 (DW_OP_fbreg -0x14) __vgic_v3_restore_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:369
~ 0000cd78: d10103ff sub sp, sp, #0x40 <- 0000754c(bl)<__vgic_v3_restore_aprs>
~ 0000cd7c: a9037bfd stp x29, x30, [sp, #48]
0000cd78 CFA:r31 r29:u r30:u
~ 0000cd80: 9100c3fd add x29, sp, #0x30
~ 0000cd84: f81f83a0 stur x0, [x29, #-8]
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd88 0xcd9c (DW_OP_breg31 0x10) lexblock:__vgic_v3_restore_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:371
~ 0000cd88: d53ccb28 mrs x8, s3_4_c12_c11_1
__vgic_v3_restore_aprs:371.8 (vgic-v3-sr.c) SbePe val = ║read_gicreg(ICH_VTR_EL2);
~ 0000cd8c: f9000be8 str x8, [sp, #16]
~ 0000cd90: f9400be8 ldr x8, [sp, #16]
~ 0000cd94: f90007e8 str x8, [sp, #8]
~ 0000cd98: f94007e8 ldr x8, [sp, #8]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd88 0xcd9c (DW_OP_breg31 0x10) lexblock:__vgic_v3_restore_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:371
__vgic_v3_restore_aprs:371.6 (vgic-v3-sr.c) sbepe val ║= read_gicreg(ICH_VTR_EL2);
~ 0000cd9c: f81f03a8 stur x8, [x29, #-16]
__vgic_v3_restore_aprs:372.16 (vgic-v3-sr.c) Sbepe nr_pre_bits = ║vtr_to_nr_pre_bits(val);
~ 0000cda0: b85f03a9 ldur w9, [x29, #-16]
~ 0000cda4: 531a7129 ubfx w9, w9, #26, #3
~ 0000cda8: 11000529 add w9, w9, #0x1
__vgic_v3_restore_aprs:372.14 (vgic-v3-sr.c) sbepe nr_pre_bits ║= vtr_to_nr_pre_bits(val);
~ 0000cdac: b81ec3a9 stur w9, [x29, #-20]
__vgic_v3_restore_aprs:374.10 (vgic-v3-sr.c) Sbepe switch (║nr_pre_bits) {
~ 0000cdb0: b85ec3a9 ldur w9, [x29, #-20]
__vgic_v3_restore_aprs:374.2 (vgic-v3-sr.c) sbepe ║switch (nr_pre_bits) {
~ 0000cdb4: 2a0903ea mov w10, w9
~ 0000cdb8: 71001929 subs w9, w9, #0x6
~ 0000cdbc: b90007ea str w10, [sp, #4]
~ ┌───0000cdc0: 540001e0 b.eq cdfc <__vgic_v3_restore_aprs+0x84> // b.none
│
~ │ ┌─0000cdc4: 14000001 b cdc8 <__vgic_v3_restore_aprs+0x50> <- 0000cdc0(b.cc-succ)<fallthrough>
│ │
~ │ └>0000cdc8: b94007e8 ldr w8, [sp, #4] <- 0000cdc4(b)<__vgic_v3_restore_aprs+0x50>
│ __vgic_v3_restore_aprs:374.2 (vgic-v3-sr.c) sbepe ║switch (nr_pre_bits) {
~ │ 0000cdcc: 71001d09 subs w9, w8, #0x7
~ ┌┼───0000cdd0: 54000201 b.ne ce10 <__vgic_v3_restore_aprs+0x98> // b.any
││
~ ││ ┌─0000cdd4: 14000001 b cdd8 <__vgic_v3_restore_aprs+0x60> <- 0000cdd0(b.cc-succ)<fallthrough>
││ │
││ │ __vgic_v3_restore_aprs:376.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap0rn(║cpu_if->vgic_ap0r[3], 3);
~ ││ └>0000cdd8: f85f83a8 ldur x8, [x29, #-8] <- 0000cdd4(b)<__vgic_v3_restore_aprs+0x60>
~ ││ 0000cddc: b9401900 ldr w0, [x8, #24]
~ ││ 0000cde0: 52800061 mov w1, #0x3 // #3
││ __vgic_v3_restore_aprs:376.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[3], 3);
~ ││ 0000cde4: 94000030 bl cea4 <__vgic_v3_write_ap0rn>
││
││ __vgic_v3_restore_aprs:377.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap0rn(║cpu_if->vgic_ap0r[2], 2);
~ ││ 0000cde8: f85f83a8 ldur x8, [x29, #-8] <- 0000cde4(bl-succ)<return>
~ ││ 0000cdec: b9401500 ldr w0, [x8, #20]
~ ││ 0000cdf0: 52800041 mov w1, #0x2 // #2
││ __vgic_v3_restore_aprs:377.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[2], 2);
~ ││ 0000cdf4: 9400002c bl cea4 <__vgic_v3_write_ap0rn>
││
~ ││ ┌─0000cdf8: 14000001 b cdfc <__vgic_v3_restore_aprs+0x84> <- 0000cdf4(bl-succ)<return>
││ │
││ │ __vgic_v3_restore_aprs:380.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap0rn(║cpu_if->vgic_ap0r[1], 1);
~ │└>└>0000cdfc: f85f83a8 ldur x8, [x29, #-8] <- 0000cdc0(b.cc)<__vgic_v3_restore_aprs+0x84>,0000cdf8(b)<__vgic_v3_restore_aprs+0x84>
~ │ 0000ce00: b9401100 ldr w0, [x8, #16]
~ │ 0000ce04: 52800021 mov w1, #0x1 // #1
│ __vgic_v3_restore_aprs:380.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[1], 1);
~ │ 0000ce08: 94000027 bl cea4 <__vgic_v3_write_ap0rn>
│
~ │ ┌─0000ce0c: 14000001 b ce10 <__vgic_v3_restore_aprs+0x98> <- 0000ce08(bl-succ)<return>
│ │
│ │ __vgic_v3_restore_aprs:383.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap0rn(║cpu_if->vgic_ap0r[0], 0);
~ └─>└>0000ce10: f85f83a8 ldur x8, [x29, #-8] <- 0000cdd0(b.cc)<__vgic_v3_restore_aprs+0x98>,0000ce0c(b)<__vgic_v3_restore_aprs+0x98>
~ 0000ce14: b9400d00 ldr w0, [x8, #12]
~ 0000ce18: 2a1f03e1 mov w1, wzr
__vgic_v3_restore_aprs:383.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[0], 0);
~ 0000ce1c: 94000022 bl cea4 <__vgic_v3_write_ap0rn>
__vgic_v3_restore_aprs:384.2 (vgic-v3-sr.c) Sbepe }
~ ┌─0000ce20: 14000001 b ce24 <__vgic_v3_restore_aprs+0xac> <- 0000ce1c(bl-succ)<return>
│
│ __vgic_v3_restore_aprs:386.10 (vgic-v3-sr.c) Sbepe switch (║nr_pre_bits) {
~ └>0000ce24: b85ec3a8 ldur w8, [x29, #-20] <- 0000ce20(b)<__vgic_v3_restore_aprs+0xac>
__vgic_v3_restore_aprs:386.2 (vgic-v3-sr.c) sbepe ║switch (nr_pre_bits) {
~ 0000ce28: 2a0803e9 mov w9, w8
~ 0000ce2c: 71001908 subs w8, w8, #0x6
~ 0000ce30: b90003e9 str w9, [sp]
~ ┌───0000ce34: 540001e0 b.eq ce70 <__vgic_v3_restore_aprs+0xf8> // b.none
│
~ │ ┌─0000ce38: 14000001 b ce3c <__vgic_v3_restore_aprs+0xc4> <- 0000ce34(b.cc-succ)<fallthrough>
│ │
~ │ └>0000ce3c: b94003e8 ldr w8, [sp] <- 0000ce38(b)<__vgic_v3_restore_aprs+0xc4>
│ __vgic_v3_restore_aprs:386.2 (vgic-v3-sr.c) sbepe ║switch (nr_pre_bits) {
~ │ 0000ce40: 71001d09 subs w9, w8, #0x7
~ ┌┼───0000ce44: 54000201 b.ne ce84 <__vgic_v3_restore_aprs+0x10c> // b.any
││
~ ││ ┌─0000ce48: 14000001 b ce4c <__vgic_v3_restore_aprs+0xd4> <- 0000ce44(b.cc-succ)<fallthrough>
││ │
││ │ __vgic_v3_restore_aprs:388.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap1rn(║cpu_if->vgic_ap1r[3], 3);
~ ││ └>0000ce4c: f85f83a8 ldur x8, [x29, #-8] <- 0000ce48(b)<__vgic_v3_restore_aprs+0xd4>
~ ││ 0000ce50: b9402900 ldr w0, [x8, #40]
~ ││ 0000ce54: 52800061 mov w1, #0x3 // #3
││ __vgic_v3_restore_aprs:388.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[3], 3);
~ ││ 0000ce58: 94000044 bl cf68 <__vgic_v3_write_ap1rn>
││
││ __vgic_v3_restore_aprs:389.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap1rn(║cpu_if->vgic_ap1r[2], 2);
~ ││ 0000ce5c: f85f83a8 ldur x8, [x29, #-8] <- 0000ce58(bl-succ)<return>
~ ││ 0000ce60: b9402500 ldr w0, [x8, #36]
~ ││ 0000ce64: 52800041 mov w1, #0x2 // #2
││ __vgic_v3_restore_aprs:389.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[2], 2);
~ ││ 0000ce68: 94000040 bl cf68 <__vgic_v3_write_ap1rn>
││
~ ││ ┌─0000ce6c: 14000001 b ce70 <__vgic_v3_restore_aprs+0xf8> <- 0000ce68(bl-succ)<return>
││ │
││ │ __vgic_v3_restore_aprs:392.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap1rn(║cpu_if->vgic_ap1r[1], 1);
~ │└>└>0000ce70: f85f83a8 ldur x8, [x29, #-8] <- 0000ce34(b.cc)<__vgic_v3_restore_aprs+0xf8>,0000ce6c(b)<__vgic_v3_restore_aprs+0xf8>
~ │ 0000ce74: b9402100 ldr w0, [x8, #32]
~ │ 0000ce78: 52800021 mov w1, #0x1 // #1
│ __vgic_v3_restore_aprs:392.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[1], 1);
~ │ 0000ce7c: 9400003b bl cf68 <__vgic_v3_write_ap1rn>
│
~ │ ┌─0000ce80: 14000001 b ce84 <__vgic_v3_restore_aprs+0x10c> <- 0000ce7c(bl-succ)<return>
│ │
│ │ __vgic_v3_restore_aprs:395.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap1rn(║cpu_if->vgic_ap1r[0], 0);
~ └─>└>0000ce84: f85f83a8 ldur x8, [x29, #-8] <- 0000ce44(b.cc)<__vgic_v3_restore_aprs+0x10c>,0000ce80(b)<__vgic_v3_restore_aprs+0x10c>
~ 0000ce88: b9401d00 ldr w0, [x8, #28]
~ 0000ce8c: 2a1f03e1 mov w1, wzr
__vgic_v3_restore_aprs:395.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[0], 0);
~ 0000ce90: 94000036 bl cf68 <__vgic_v3_write_ap1rn>
__vgic_v3_restore_aprs:396.2 (vgic-v3-sr.c) Sbepe }
~ ┌─0000ce94: 14000001 b ce98 <__vgic_v3_restore_aprs+0x120> <- 0000ce90(bl-succ)<return>
│
│ __vgic_v3_restore_aprs:397.1 (vgic-v3-sr.c) Sbepe ║}
~ └>0000ce98: a9437bfd ldp x29, x30, [sp, #48] <- 0000ce94(b)<__vgic_v3_restore_aprs+0x120>
~ 0000ce9c: 910103ff add sp, sp, #0x40
0000cd84 CFA:r29+16 r29:c-16 r30:c-8
~ 0000cea0: d65f03c0 ret
-cpu_if param pointer(struct vgic_v3_cpu_if<99433>/<a81cf>) 0xcd78 0xcea4 (DW_OP_fbreg -0x8) __vgic_v3_restore_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:366
-val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcd78 0xcea4 (DW_OP_fbreg -0x10) __vgic_v3_restore_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:368
-nr_pre_bits var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcd78 0xcea4 (DW_OP_fbreg -0x14) __vgic_v3_restore_aprs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:369
**0000cea4 <__vgic_v3_write_ap0rn>:
+ __vgic_v3_write_ap0rn params:
+val param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcea4 0xcf68 (DW_OP_fbreg 0x2c)
+n param int (base type, DW_ATE_signed size:4) 0xcea4 0xcf68 (DW_OP_fbreg 0x28)
__vgic_v3_write_ap0rn:116.0 (vgic-v3-sr.c) Sbepe ║{
0000cea4 CFA:r31
+val param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcea4 0xcf68 (DW_OP_fbreg 0x2c) __vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:115
+n param int (base type, DW_ATE_signed size:4) 0xcea4 0xcf68 (DW_OP_fbreg 0x28) __vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:115
~ 0000cea4: d100c3ff sub sp, sp, #0x30 <- 0000cde4(bl)<__vgic_v3_write_ap0rn>,0000cdf4(bl)<__vgic_v3_write_ap0rn>,0000ce08(bl)<__vgic_v3_write_ap0rn>,0000ce1c(bl)<__vgic_v3_write_ap0rn>,0000eac0(bl)<__vgic_v3_write_ap0rn>,0000ed0c(bl)<__vgic_v3_write_ap0rn>,0000f05c(bl)<__vgic_v3_write_ap0rn>
~ 0000cea8: b9002fe0 str w0, [sp, #44]
~ 0000ceac: b9002be1 str w1, [sp, #40]
__vgic_v3_write_ap0rn:117.10 (vgic-v3-sr.c) SbePe switch (║n) {
~ 0000ceb0: b9402be8 ldr w8, [sp, #40]
~ 0000ceb4: 2a0803e9 mov w9, w8
~ 0000ceb8: 2a0903e8 mov w8, w9
__vgic_v3_write_ap0rn:117.2 (vgic-v3-sr.c) sbepe ║switch (n) {
~ 0000cebc: 71000d08 subs w8, w8, #0x3
~ 0000cec0: f90003e9 str x9, [sp]
~ ┌───────────0000cec4: 540004e8 b.hi cf60 <__vgic_v3_write_ap0rn+0xbc> // b.pmore
│
~ │ 0000cec8: f0000048 adrp x8, 17000 <___kvm_hyp_init+0x3c> <- 0000cec4(b.cc-succ)<fallthrough>
~ │ 0000cecc: 913db108 add x8, x8, #0xf6c
~ │ 0000ced0: f94003eb ldr x11, [sp]
~ │ 0000ced4: b8ab790a ldrsw x10, [x8, x11, lsl #2]
~ │ 0000ced8: 8b0a0109 add x9, x8, x10
│
~ │ X0000cedc: d61f0120 br x9 -> 0000cedc<indirect0> <- 0000cedc(br)<indirect0>
│ __vgic_v3_write_ap0rn:119.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_AP0R0_EL2);
~ │ ┌─0000cee0: 14000001 b cee4 <__vgic_v3_write_ap0rn+0x40>
│ │
│ │ __vgic_v3_write_ap0rn:119.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_AP0R0_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcee4 0xcefc (DW_OP_fbreg 0x20) lexblock:__vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:119
~ │ └>0000cee4: b9402fe8 ldr w8, [sp, #44] <- 0000cee0(b)<__vgic_v3_write_ap0rn+0x40>
~ │ 0000cee8: 2a0803e9 mov w9, w8
~ │ 0000ceec: f90013e9 str x9, [sp, #32]
~ │ 0000cef0: f94013e9 ldr x9, [sp, #32]
~ │ 0000cef4: d51cc809 msr s3_4_c12_c8_0, x9
~ │ ┌─0000cef8: 14000001 b cefc <__vgic_v3_write_ap0rn+0x58>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcee4 0xcefc (DW_OP_fbreg 0x20) lexblock:__vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:119
│ │
│ │ __vgic_v3_write_ap0rn:120.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ ┌───────└>0000cefc: 14000019 b cf60 <__vgic_v3_write_ap0rn+0xbc> <- 0000cef8(b)<__vgic_v3_write_ap0rn+0x58>
│ │ __vgic_v3_write_ap0rn:122.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_AP0R1_EL2);
~ │ │ ┌─0000cf00: 14000001 b cf04 <__vgic_v3_write_ap0rn+0x60>
│ │ │
│ │ │ __vgic_v3_write_ap0rn:122.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_AP0R1_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcf04 0xcf1c (DW_OP_fbreg 0x18) lexblock:__vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:122
~ │ │ └>0000cf04: b9402fe8 ldr w8, [sp, #44] <- 0000cf00(b)<__vgic_v3_write_ap0rn+0x60>
~ │ │ 0000cf08: 2a0803e9 mov w9, w8
~ │ │ 0000cf0c: f9000fe9 str x9, [sp, #24]
~ │ │ 0000cf10: f9400fe9 ldr x9, [sp, #24]
~ │ │ 0000cf14: d51cc829 msr s3_4_c12_c8_1, x9
~ │ │ ┌─0000cf18: 14000001 b cf1c <__vgic_v3_write_ap0rn+0x78>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcf04 0xcf1c (DW_OP_fbreg 0x18) lexblock:__vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:122
│ │ │
│ │ │ __vgic_v3_write_ap0rn:123.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ┌─────└>0000cf1c: 14000011 b cf60 <__vgic_v3_write_ap0rn+0xbc> <- 0000cf18(b)<__vgic_v3_write_ap0rn+0x78>
│ │ │ __vgic_v3_write_ap0rn:125.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_AP0R2_EL2);
~ │ │ │ ┌─0000cf20: 14000001 b cf24 <__vgic_v3_write_ap0rn+0x80>
│ │ │ │
│ │ │ │ __vgic_v3_write_ap0rn:125.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_AP0R2_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcf24 0xcf3c (DW_OP_fbreg 0x10) lexblock:__vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:125
~ │ │ │ └>0000cf24: b9402fe8 ldr w8, [sp, #44] <- 0000cf20(b)<__vgic_v3_write_ap0rn+0x80>
~ │ │ │ 0000cf28: 2a0803e9 mov w9, w8
~ │ │ │ 0000cf2c: f9000be9 str x9, [sp, #16]
~ │ │ │ 0000cf30: f9400be9 ldr x9, [sp, #16]
~ │ │ │ 0000cf34: d51cc849 msr s3_4_c12_c8_2, x9
~ │ │ │ ┌─0000cf38: 14000001 b cf3c <__vgic_v3_write_ap0rn+0x98>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcf24 0xcf3c (DW_OP_fbreg 0x10) lexblock:__vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:125
│ │ │ │
│ │ │ │ __vgic_v3_write_ap0rn:126.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ ┌───└>0000cf3c: 14000009 b cf60 <__vgic_v3_write_ap0rn+0xbc> <- 0000cf38(b)<__vgic_v3_write_ap0rn+0x98>
│ │ │ │ __vgic_v3_write_ap0rn:128.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_AP0R3_EL2);
~ │ │ │ │ ┌─0000cf40: 14000001 b cf44 <__vgic_v3_write_ap0rn+0xa0>
│ │ │ │ │
│ │ │ │ │ __vgic_v3_write_ap0rn:128.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_AP0R3_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcf44 0xcf5c (DW_OP_fbreg 0x8) lexblock:__vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:128
~ │ │ │ │ └>0000cf44: b9402fe8 ldr w8, [sp, #44] <- 0000cf40(b)<__vgic_v3_write_ap0rn+0xa0>
~ │ │ │ │ 0000cf48: 2a0803e9 mov w9, w8
~ │ │ │ │ 0000cf4c: f90007e9 str x9, [sp, #8]
~ │ │ │ │ 0000cf50: f94007e9 ldr x9, [sp, #8]
~ │ │ │ │ 0000cf54: d51cc869 msr s3_4_c12_c8_3, x9
~ │ │ │ │ ┌─0000cf58: 14000001 b cf5c <__vgic_v3_write_ap0rn+0xb8>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcf44 0xcf5c (DW_OP_fbreg 0x8) lexblock:__vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:128
│ │ │ │ │
│ │ │ │ │ __vgic_v3_write_ap0rn:129.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ ┌─└>0000cf5c: 14000001 b cf60 <__vgic_v3_write_ap0rn+0xbc> <- 0000cf58(b)<__vgic_v3_write_ap0rn+0xb8>
│ │ │ │ │
│ │ │ │ │ __vgic_v3_write_ap0rn:131.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>└>└>└──>0000cf60: 9100c3ff add sp, sp, #0x30 <- 0000cec4(b.cc)<__vgic_v3_write_ap0rn+0xbc>,0000cefc(b)<__vgic_v3_write_ap0rn+0xbc>,0000cf1c(b)<__vgic_v3_write_ap0rn+0xbc>,0000cf3c(b)<__vgic_v3_write_ap0rn+0xbc>,0000cf5c(b)<__vgic_v3_write_ap0rn+0xbc>
0000cea8 CFA:r31+48
~ 0000cf64: d65f03c0 ret
-val param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcea4 0xcf68 (DW_OP_fbreg 0x2c) __vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:115
-n param int (base type, DW_ATE_signed size:4) 0xcea4 0xcf68 (DW_OP_fbreg 0x28) __vgic_v3_write_ap0rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:115
**0000cf68 <__vgic_v3_write_ap1rn>:
+ __vgic_v3_write_ap1rn params:
+val param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcf68 0xd02c (DW_OP_fbreg 0x2c)
+n param int (base type, DW_ATE_signed size:4) 0xcf68 0xd02c (DW_OP_fbreg 0x28)
__vgic_v3_write_ap1rn:134.0 (vgic-v3-sr.c) Sbepe ║{
0000cf68 CFA:r31
+val param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcf68 0xd02c (DW_OP_fbreg 0x2c) __vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:133
+n param int (base type, DW_ATE_signed size:4) 0xcf68 0xd02c (DW_OP_fbreg 0x28) __vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:133
~ 0000cf68: d100c3ff sub sp, sp, #0x30 <- 0000ce58(bl)<__vgic_v3_write_ap1rn>,0000ce68(bl)<__vgic_v3_write_ap1rn>,0000ce7c(bl)<__vgic_v3_write_ap1rn>,0000ce90(bl)<__vgic_v3_write_ap1rn>,0000eaec(bl)<__vgic_v3_write_ap1rn>,0000ed50(bl)<__vgic_v3_write_ap1rn>,0000f06c(bl)<__vgic_v3_write_ap1rn>
~ 0000cf6c: b9002fe0 str w0, [sp, #44]
~ 0000cf70: b9002be1 str w1, [sp, #40]
__vgic_v3_write_ap1rn:135.10 (vgic-v3-sr.c) SbePe switch (║n) {
~ 0000cf74: b9402be8 ldr w8, [sp, #40]
~ 0000cf78: 2a0803e9 mov w9, w8
~ 0000cf7c: 2a0903e8 mov w8, w9
__vgic_v3_write_ap1rn:135.2 (vgic-v3-sr.c) sbepe ║switch (n) {
~ 0000cf80: 71000d08 subs w8, w8, #0x3
~ 0000cf84: f90003e9 str x9, [sp]
~ ┌───────────0000cf88: 540004e8 b.hi d024 <__vgic_v3_write_ap1rn+0xbc> // b.pmore
│
~ │ 0000cf8c: f0000048 adrp x8, 17000 <___kvm_hyp_init+0x3c> <- 0000cf88(b.cc-succ)<fallthrough>
~ │ 0000cf90: 913df108 add x8, x8, #0xf7c
~ │ 0000cf94: f94003eb ldr x11, [sp]
~ │ 0000cf98: b8ab790a ldrsw x10, [x8, x11, lsl #2]
~ │ 0000cf9c: 8b0a0109 add x9, x8, x10
│
~ │ X0000cfa0: d61f0120 br x9 -> 0000cfa0<indirect0> <- 0000cfa0(br)<indirect0>
│ __vgic_v3_write_ap1rn:137.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_AP1R0_EL2);
~ │ ┌─0000cfa4: 14000001 b cfa8 <__vgic_v3_write_ap1rn+0x40>
│ │
│ │ __vgic_v3_write_ap1rn:137.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_AP1R0_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcfa8 0xcfc0 (DW_OP_fbreg 0x20) lexblock:__vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:137
~ │ └>0000cfa8: b9402fe8 ldr w8, [sp, #44] <- 0000cfa4(b)<__vgic_v3_write_ap1rn+0x40>
~ │ 0000cfac: 2a0803e9 mov w9, w8
~ │ 0000cfb0: f90013e9 str x9, [sp, #32]
~ │ 0000cfb4: f94013e9 ldr x9, [sp, #32]
~ │ 0000cfb8: d51cc909 msr s3_4_c12_c9_0, x9
~ │ ┌─0000cfbc: 14000001 b cfc0 <__vgic_v3_write_ap1rn+0x58>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcfa8 0xcfc0 (DW_OP_fbreg 0x20) lexblock:__vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:137
│ │
│ │ __vgic_v3_write_ap1rn:138.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ ┌───────└>0000cfc0: 14000019 b d024 <__vgic_v3_write_ap1rn+0xbc> <- 0000cfbc(b)<__vgic_v3_write_ap1rn+0x58>
│ │ __vgic_v3_write_ap1rn:140.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_AP1R1_EL2);
~ │ │ ┌─0000cfc4: 14000001 b cfc8 <__vgic_v3_write_ap1rn+0x60>
│ │ │
│ │ │ __vgic_v3_write_ap1rn:140.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_AP1R1_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcfc8 0xcfe0 (DW_OP_fbreg 0x18) lexblock:__vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:140
~ │ │ └>0000cfc8: b9402fe8 ldr w8, [sp, #44] <- 0000cfc4(b)<__vgic_v3_write_ap1rn+0x60>
~ │ │ 0000cfcc: 2a0803e9 mov w9, w8
~ │ │ 0000cfd0: f9000fe9 str x9, [sp, #24]
~ │ │ 0000cfd4: f9400fe9 ldr x9, [sp, #24]
~ │ │ 0000cfd8: d51cc929 msr s3_4_c12_c9_1, x9
~ │ │ ┌─0000cfdc: 14000001 b cfe0 <__vgic_v3_write_ap1rn+0x78>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcfc8 0xcfe0 (DW_OP_fbreg 0x18) lexblock:__vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:140
│ │ │
│ │ │ __vgic_v3_write_ap1rn:141.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ┌─────└>0000cfe0: 14000011 b d024 <__vgic_v3_write_ap1rn+0xbc> <- 0000cfdc(b)<__vgic_v3_write_ap1rn+0x78>
│ │ │ __vgic_v3_write_ap1rn:143.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_AP1R2_EL2);
~ │ │ │ ┌─0000cfe4: 14000001 b cfe8 <__vgic_v3_write_ap1rn+0x80>
│ │ │ │
│ │ │ │ __vgic_v3_write_ap1rn:143.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_AP1R2_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcfe8 0xd000 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:143
~ │ │ │ └>0000cfe8: b9402fe8 ldr w8, [sp, #44] <- 0000cfe4(b)<__vgic_v3_write_ap1rn+0x80>
~ │ │ │ 0000cfec: 2a0803e9 mov w9, w8
~ │ │ │ 0000cff0: f9000be9 str x9, [sp, #16]
~ │ │ │ 0000cff4: f9400be9 ldr x9, [sp, #16]
~ │ │ │ 0000cff8: d51cc949 msr s3_4_c12_c9_2, x9
~ │ │ │ ┌─0000cffc: 14000001 b d000 <__vgic_v3_write_ap1rn+0x98>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xcfe8 0xd000 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:143
│ │ │ │
│ │ │ │ __vgic_v3_write_ap1rn:144.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ ┌───└>0000d000: 14000009 b d024 <__vgic_v3_write_ap1rn+0xbc> <- 0000cffc(b)<__vgic_v3_write_ap1rn+0x98>
│ │ │ │ __vgic_v3_write_ap1rn:146.3 (vgic-v3-sr.c) Sbepe ║write_gicreg(val, ICH_AP1R3_EL2);
~ │ │ │ │ ┌─0000d004: 14000001 b d008 <__vgic_v3_write_ap1rn+0xa0>
│ │ │ │ │
│ │ │ │ │ __vgic_v3_write_ap1rn:146.3 (vgic-v3-sr.c) sbepe ║write_gicreg(val, ICH_AP1R3_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd008 0xd020 (DW_OP_fbreg 0x8) lexblock:__vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:146
~ │ │ │ │ └>0000d008: b9402fe8 ldr w8, [sp, #44] <- 0000d004(b)<__vgic_v3_write_ap1rn+0xa0>
~ │ │ │ │ 0000d00c: 2a0803e9 mov w9, w8
~ │ │ │ │ 0000d010: f90007e9 str x9, [sp, #8]
~ │ │ │ │ 0000d014: f94007e9 ldr x9, [sp, #8]
~ │ │ │ │ 0000d018: d51cc969 msr s3_4_c12_c9_3, x9
~ │ │ │ │ ┌─0000d01c: 14000001 b d020 <__vgic_v3_write_ap1rn+0xb8>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd008 0xd020 (DW_OP_fbreg 0x8) lexblock:__vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:146
│ │ │ │ │
│ │ │ │ │ __vgic_v3_write_ap1rn:147.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ │ │ ┌─└>0000d020: 14000001 b d024 <__vgic_v3_write_ap1rn+0xbc> <- 0000d01c(b)<__vgic_v3_write_ap1rn+0xb8>
│ │ │ │ │
│ │ │ │ │ __vgic_v3_write_ap1rn:149.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>└>└>└──>0000d024: 9100c3ff add sp, sp, #0x30 <- 0000cf88(b.cc)<__vgic_v3_write_ap1rn+0xbc>,0000cfc0(b)<__vgic_v3_write_ap1rn+0xbc>,0000cfe0(b)<__vgic_v3_write_ap1rn+0xbc>,0000d000(b)<__vgic_v3_write_ap1rn+0xbc>,0000d020(b)<__vgic_v3_write_ap1rn+0xbc>
0000cf6c CFA:r31+48
~ 0000d028: d65f03c0 ret
-val param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xcf68 0xd02c (DW_OP_fbreg 0x2c) __vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:133
-n param int (base type, DW_ATE_signed size:4) 0xcf68 0xd02c (DW_OP_fbreg 0x28) __vgic_v3_write_ap1rn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:133
**0000d02c <__vgic_v3_init_lrs>:
+ __vgic_v3_init_lrs params: none
__vgic_v3_init_lrs:400.0 (vgic-v3-sr.c) Sbepe ║{
+max_lr_idx var int (base type, DW_ATE_signed size:4) 0xd02c 0xd0a4 (DW_OP_fbreg -0x4) __vgic_v3_init_lrs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:401
+i var int (base type, DW_ATE_signed size:4) 0xd02c 0xd0a4 (DW_OP_breg31 0x4) __vgic_v3_init_lrs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:402
~ 0000d02c: d100c3ff sub sp, sp, #0x30 <- 00007474(bl)<__vgic_v3_init_lrs>
~ 0000d030: a9027bfd stp x29, x30, [sp, #32]
0000d02c CFA:r31 r29:u r30:u
~ 0000d034: 910083fd add x29, sp, #0x20
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd038 0xd04c (DW_OP_breg31 0x10) lexblock:__vgic_v3_init_lrs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:401
~ 0000d038: d53ccb28 mrs x8, s3_4_c12_c11_1
__vgic_v3_init_lrs:401.19 (vgic-v3-sr.c) SbePe int max_lr_idx = ║vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2));
~ 0000d03c: f9000be8 str x8, [sp, #16]
~ 0000d040: f9400be8 ldr x8, [sp, #16]
~ 0000d044: f90007e8 str x8, [sp, #8]
~ 0000d048: b9400be9 ldr w9, [sp, #8]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd038 0xd04c (DW_OP_breg31 0x10) lexblock:__vgic_v3_init_lrs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:401
__vgic_v3_init_lrs:401.19 (vgic-v3-sr.c) sbepe int max_lr_idx = ║vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2));
~ 0000d04c: 12000d29 and w9, w9, #0xf
~ 0000d050: 2a0903e0 mov w0, w9
__vgic_v3_init_lrs:401.6 (vgic-v3-sr.c) sbepe int ║max_lr_idx = vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2));
~ 0000d054: b81fc3a0 stur w0, [x29, #-4]
~ 0000d058: 2a1f03e9 mov w9, wzr
__vgic_v3_init_lrs:404.9 (vgic-v3-sr.c) Sbepe for (i ║= 0; i <= max_lr_idx; i++)
~ 0000d05c: b90007e9 str w9, [sp, #4]
__vgic_v3_init_lrs:404.7 (vgic-v3-sr.c) sbepe for (║i = 0; i <= max_lr_idx; i++)
~ ┌─0000d060: 14000001 b d064 <__vgic_v3_init_lrs+0x38>
│
│ __vgic_v3_init_lrs:404.14 (vgic-v3-sr.c) sbepe for (i = 0; ║i <= max_lr_idx; i++)
~ ╔>└>0000d064: b94007e8 ldr w8, [sp, #4] <- 0000d060(b)<__vgic_v3_init_lrs+0x38>,v0000d094(b)<__vgic_v3_init_lrs+0x38>
║ __vgic_v3_init_lrs:404.19 (vgic-v3-sr.c) sbepe for (i = 0; i <= ║max_lr_idx; i++)
~ ║ 0000d068: b85fc3a9 ldur w9, [x29, #-4]
║ __vgic_v3_init_lrs:404.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i <= max_lr_idx; i++)
~ ║ 0000d06c: 6b090108 subs w8, w8, w9
~ ║┌──0000d070: 5400014c b.gt d098 <__vgic_v3_init_lrs+0x6c>
║│
~ ║│┌─0000d074: 14000001 b d078 <__vgic_v3_init_lrs+0x4c> <- 0000d070(b.cc-succ)<fallthrough>
║││
║││ __vgic_v3_init_lrs:405.22 (vgic-v3-sr.c) Sbepe __gic_v3_set_lr(0, ║i);
~ ║│└>0000d078: b94007e1 ldr w1, [sp, #4] <- 0000d074(b)<__vgic_v3_init_lrs+0x4c>
~ ║│ 0000d07c: aa1f03e0 mov x0, xzr
║│ __vgic_v3_init_lrs:405.3 (vgic-v3-sr.c) sbepe ║__gic_v3_set_lr(0, i);
~ ║│ 0000d080: 97fffd51 bl c5c4 <__gic_v3_set_lr>
║│
~ ║│┌─0000d084: 14000001 b d088 <__vgic_v3_init_lrs+0x5c> <- 0000d080(bl-succ)<return>
║││
║││ __vgic_v3_init_lrs:404.32 (vgic-v3-sr.c) Sbepe for (i = 0; i <= max_lr_idx; i║++)
~ ║│└>0000d088: b94007e8 ldr w8, [sp, #4] <- 0000d084(b)<__vgic_v3_init_lrs+0x5c>
~ ║│ 0000d08c: 11000508 add w8, w8, #0x1
~ ║│ 0000d090: b90007e8 str w8, [sp, #4]
║│ __vgic_v3_init_lrs:404.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i <= max_lr_idx; i++)
~ ╚╪══0000d094: 17fffff4 b d064 <__vgic_v3_init_lrs+0x38>
│
│ __vgic_v3_init_lrs:406.1 (vgic-v3-sr.c) Sbepe ║}
~ └─>0000d098: a9427bfd ldp x29, x30, [sp, #32] <- 0000d070(b.cc)<__vgic_v3_init_lrs+0x6c>
~ 0000d09c: 9100c3ff add sp, sp, #0x30
0000d038 CFA:r29+16 r29:c-16 r30:c-8
~ 0000d0a0: d65f03c0 ret
-max_lr_idx var int (base type, DW_ATE_signed size:4) 0xd02c 0xd0a4 (DW_OP_fbreg -0x4) __vgic_v3_init_lrs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:401
-i var int (base type, DW_ATE_signed size:4) 0xd02c 0xd0a4 (DW_OP_breg31 0x4) __vgic_v3_init_lrs:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:402
**0000d0a4 <__vgic_v3_get_ich_vtr_el2>:
+ __vgic_v3_get_ich_vtr_el2 params: none
__vgic_v3_get_ich_vtr_el2:409.0 (vgic-v3-sr.c) Sbepe ║{
0000d0a4 CFA:r31
~ 0000d0a4: d10043ff sub sp, sp, #0x10 <- 000073fc(bl)<__vgic_v3_get_ich_vtr_el2>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd0a8 0xd0bc (DW_OP_fbreg 0x8) lexblock:__vgic_v3_get_ich_vtr_el2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:410
~ 0000d0a8: d53ccb28 mrs x8, s3_4_c12_c11_1
__vgic_v3_get_ich_vtr_el2:410.9 (vgic-v3-sr.c) SbePe return ║read_gicreg(ICH_VTR_EL2);
~ 0000d0ac: f90007e8 str x8, [sp, #8]
~ 0000d0b0: f94007e8 ldr x8, [sp, #8]
~ 0000d0b4: f90003e8 str x8, [sp]
~ 0000d0b8: f94003e0 ldr x0, [sp]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd0a8 0xd0bc (DW_OP_fbreg 0x8) lexblock:__vgic_v3_get_ich_vtr_el2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:410
__vgic_v3_get_ich_vtr_el2:410.2 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_VTR_EL2);
~ 0000d0bc: 910043ff add sp, sp, #0x10
0000d0a8 CFA:r31+16
~ 0000d0c0: d65f03c0 ret
**0000d0c4 <__vgic_v3_read_vmcr>:
+ __vgic_v3_read_vmcr params: none
__vgic_v3_read_vmcr:414.0 (vgic-v3-sr.c) Sbepe ║{
0000d0c4 CFA:r31
~ 0000d0c4: d10043ff sub sp, sp, #0x10 <- 00007424(bl)<__vgic_v3_read_vmcr>,0000d714(bl)<__vgic_v3_read_vmcr>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd0c8 0xd0dc (DW_OP_fbreg 0x8) lexblock:__vgic_v3_read_vmcr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:415
~ 0000d0c8: d53ccbe8 mrs x8, s3_4_c12_c11_7
__vgic_v3_read_vmcr:415.9 (vgic-v3-sr.c) SbePe return ║read_gicreg(ICH_VMCR_EL2);
~ 0000d0cc: f90007e8 str x8, [sp, #8]
~ 0000d0d0: f94007e8 ldr x8, [sp, #8]
~ 0000d0d4: f90003e8 str x8, [sp]
~ 0000d0d8: f94003e0 ldr x0, [sp]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd0c8 0xd0dc (DW_OP_fbreg 0x8) lexblock:__vgic_v3_read_vmcr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:415
__vgic_v3_read_vmcr:415.2 (vgic-v3-sr.c) sbepe ║return read_gicreg(ICH_VMCR_EL2);
~ 0000d0dc: 910043ff add sp, sp, #0x10
0000d0c8 CFA:r31+16
~ 0000d0e0: d65f03c0 ret
**0000d0e4 <__vgic_v3_write_vmcr>:
+ __vgic_v3_write_vmcr params:
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd0e4 0xd110 (DW_OP_fbreg 0xc)
__vgic_v3_write_vmcr:419.0 (vgic-v3-sr.c) Sbepe ║{
0000d0e4 CFA:r31
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd0e4 0xd110 (DW_OP_fbreg 0xc) __vgic_v3_write_vmcr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:418
~ 0000d0e4: d10043ff sub sp, sp, #0x10 <- 00007454(bl)<__vgic_v3_write_vmcr>,0000dc04(bl)<__vgic_v3_write_vmcr>,0000dd7c(bl)<__vgic_v3_write_vmcr>,0000e100(bl)<__vgic_v3_write_vmcr>,0000e26c(bl)<__vgic_v3_write_vmcr>
~ 0000d0e8: b9000fe0 str w0, [sp, #12]
__vgic_v3_write_vmcr:420.2 (vgic-v3-sr.c) SbePe ║write_gicreg(vmcr, ICH_VMCR_EL2);
~ ┌─0000d0ec: 14000001 b d0f0 <__vgic_v3_write_vmcr+0xc>
│
│ __vgic_v3_write_vmcr:420.2 (vgic-v3-sr.c) sbepe ║write_gicreg(vmcr, ICH_VMCR_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd0f0 0xd108 (DW_OP_fbreg 0x0) lexblock:__vgic_v3_write_vmcr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:420
~ └>0000d0f0: b9400fe8 ldr w8, [sp, #12] <- 0000d0ec(b)<__vgic_v3_write_vmcr+0xc>
~ 0000d0f4: 2a0803e9 mov w9, w8
~ 0000d0f8: f90003e9 str x9, [sp]
~ 0000d0fc: f94003e9 ldr x9, [sp]
~ 0000d100: d51ccbe9 msr s3_4_c12_c11_7, x9
~ ┌─0000d104: 14000001 b d108 <__vgic_v3_write_vmcr+0x24>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd0f0 0xd108 (DW_OP_fbreg 0x0) lexblock:__vgic_v3_write_vmcr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:420
│
│ __vgic_v3_write_vmcr:421.1 (vgic-v3-sr.c) Sbepe ║}
~ └>0000d108: 910043ff add sp, sp, #0x10 <- 0000d104(b)<__vgic_v3_write_vmcr+0x24>
0000d0e8 CFA:r31+16
~ 0000d10c: d65f03c0 ret
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd0e4 0xd110 (DW_OP_fbreg 0xc) __vgic_v3_write_vmcr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:418
**0000d110 <__vgic_v3_perform_cpuif_access>:
+ __vgic_v3_perform_cpuif_access params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd110 0xd780 (DW_OP_breg31 0x30)
__vgic_v3_perform_cpuif_access:975.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd110 0xd780 (DW_OP_breg31 0x30) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:974
+rt var int (base type, DW_ATE_signed size:4) 0xd110 0xd780 (DW_OP_breg31 0x2c) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:976
+esr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd110 0xd780 (DW_OP_breg31 0x28) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:977
+vmcr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd110 0xd780 (DW_OP_breg31 0x24) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:978
+fn var pointer(subroutine(prototyped no type(pointer(struct kvm_vcpu<99433>/<9a302>),typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))),int (base type, DW_ATE_signed size:4))) 0xd110 0xd780 (DW_OP_breg31 0x18) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:979
+is_read var typedef(bool=_Bool (base type, DW_ATE_boolean size:1)) 0xd110 0xd780 (DW_OP_breg31 0x14) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:980
+sysreg var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd110 0xd780 (DW_OP_breg31 0x10) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:981
~ 0000d110: d10283ff sub sp, sp, #0xa0 <- 000031bc(bl)<__vgic_v3_perform_cpuif_access>
~ 0000d114: a9097bfd stp x29, x30, [sp, #144]
0000d110 CFA:r31 r29:u r30:u
~ 0000d118: 910243fd add x29, sp, #0x90
~ 0000d11c: f9001be0 str x0, [sp, #48]
__vgic_v3_perform_cpuif_access:983.25 (vgic-v3-sr.c) SbePe esr = kvm_vcpu_get_esr(║vcpu);
~ 0000d120: f9401be8 ldr x8, [sp, #48]
~ 0000d124: f90023e8 str x8, [sp, #64]
f: 0xd128 0xd130 kvm_vcpu_get_esr inlined from __vgic_v3_perform_cpuif_access:983 (vgic-v3-sr.c) <a85f6>:
f kvm_vcpu_get_esr:224.9 (kvm_emulate.h) Sbepe return ║vcpu->arch.fault.esr_el2;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd128 0xd130 (DW_OP_breg31 0x40) kvm_vcpu_get_esr(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~f 0000d128: f94023e8 ldr x8, [sp, #64]
f kvm_vcpu_get_esr:224.26 (kvm_emulate.h) sbepe return vcpu->arch.fault.║esr_el2;
~f 0000d12c: b9488909 ldr w9, [x8, #2184]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd128 0xd130 (DW_OP_breg31 0x40) kvm_vcpu_get_esr(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
__vgic_v3_perform_cpuif_access:983.6 (vgic-v3-sr.c) Sbepe esr ║= kvm_vcpu_get_esr(vcpu);
~ 0000d130: b9002be9 str w9, [sp, #40]
__vgic_v3_perform_cpuif_access:984.25 (vgic-v3-sr.c) Sbepe if (vcpu_mode_is_32bit(║vcpu)) {
~ 0000d134: f9401be8 ldr x8, [sp, #48]
~ 0000d138: f90027e8 str x8, [sp, #72]
g: 0xd13c 0xd148 vcpu_mode_is_32bit inlined from __vgic_v3_perform_cpuif_access:984 (vgic-v3-sr.c) <a8615>:
g vcpu_mode_is_32bit:142.23 (kvm_emulate.h) Sbepe return !!(*vcpu_cpsr(║vcpu) & PSR_MODE32_BIT);
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd13c 0xd148 (DW_OP_breg31 0x48) vcpu_mode_is_32bit(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~g 0000d13c: f94027e8 ldr x8, [sp, #72]
~g 0000d140: f81c03a8 stur x8, [x29, #-64]
h: 0xd144 0xd148 vcpu_cpsr inlined from vcpu_mode_is_32bit:142 (kvm_emulate.h) <a8633>:<a8615>:
gh vcpu_cpsr:137.27 (kvm_emulate.h) Sbepe return (unsigned long *)&║vcpu_gp_regs(vcpu)->pstate;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd144 0xd148 (DW_OP_fbreg -0x40) vcpu_cpsr(inlined):vcpu_mode_is_32bit(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~gh 0000d144: f85c03a8 ldur x8, [x29, #-64]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd13c 0xd148 (DW_OP_breg31 0x48) vcpu_mode_is_32bit(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd144 0xd148 (DW_OP_fbreg -0x40) vcpu_cpsr(inlined):vcpu_mode_is_32bit(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
__vgic_v3_perform_cpuif_access:984.6 (vgic-v3-sr.c) Sbepe if (║vcpu_mode_is_32bit(vcpu)) {
~ 0000d148: 3949a109 ldrb w9, [x8, #616]
~ ┌────0000d14c: 36200549 tbz w9, #4, d1f4 <__vgic_v3_perform_cpuif_access+0xe4>
│
~ │ ┌─0000d150: 14000001 b d154 <__vgic_v3_perform_cpuif_access+0x44> <- 0000d14c(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_perform_cpuif_access:985.28 (vgic-v3-sr.c) Sbepe if (!kvm_condition_valid(║vcpu)) {
~ │ └>0000d154: f9401be8 ldr x8, [sp, #48] <- 0000d150(b)<__vgic_v3_perform_cpuif_access+0x44>
~ │ 0000d158: f81c83a8 stur x8, [x29, #-56]
i: 0xd15c 0xd1a0 kvm_condition_valid inlined from __vgic_v3_perform_cpuif_access:985 (vgic-v3-sr.c) <a8651>:
i │ kvm_condition_valid:147.25 (kvm_emulate.h) Sbepe if (vcpu_mode_is_32bit(║vcpu))
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd15c 0xd1a0 (DW_OP_fbreg -0x38) kvm_condition_valid(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~i │ 0000d15c: f85c83a8 ldur x8, [x29, #-56]
~i │ 0000d160: f81d83a8 stur x8, [x29, #-40]
j: 0xd164 0xd170 vcpu_mode_is_32bit inlined from kvm_condition_valid:147 (kvm_emulate.h) <a866e>:<a8651>:
ij │ vcpu_mode_is_32bit:142.23 (kvm_emulate.h) Sbepe return !!(*vcpu_cpsr(║vcpu) & PSR_MODE32_BIT);
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd164 0xd170 (DW_OP_fbreg -0x28) vcpu_mode_is_32bit(inlined):kvm_condition_valid(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~ij │ 0000d164: f85d83a8 ldur x8, [x29, #-40]
~ij │ 0000d168: f81e03a8 stur x8, [x29, #-32]
k: 0xd16c 0xd170 vcpu_cpsr inlined from vcpu_mode_is_32bit:142 (kvm_emulate.h) <a868a>:<a866e>:<a8651>:
ijk │ vcpu_cpsr:137.27 (kvm_emulate.h) Sbepe return (unsigned long *)&║vcpu_gp_regs(vcpu)->pstate;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd16c 0xd170 (DW_OP_fbreg -0x20) vcpu_cpsr(inlined):vcpu_mode_is_32bit(inlined):kvm_condition_valid(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~ijk │ 0000d16c: f85e03a8 ldur x8, [x29, #-32]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd164 0xd170 (DW_OP_fbreg -0x28) vcpu_mode_is_32bit(inlined):kvm_condition_valid(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd16c 0xd170 (DW_OP_fbreg -0x20) vcpu_cpsr(inlined):vcpu_mode_is_32bit(inlined):kvm_condition_valid(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
i │ kvm_condition_valid:147.6 (kvm_emulate.h) Sbepe if (║vcpu_mode_is_32bit(vcpu))
~i │ 0000d170: 3949a109 ldrb w9, [x8, #616]
~i │ ┌──0000d174: 362000e9 tbz w9, #4, d190 <__vgic_v3_perform_cpuif_access+0x80>
│ │
~i │ │┌─0000d178: 14000001 b d17c <__vgic_v3_perform_cpuif_access+0x6c> <- 0000d174(b.cc-succ)<fallthrough>
│ ││
i │ ││ kvm_condition_valid:148.32 (kvm_emulate.h) Sbepe return kvm_condition_valid32(║vcpu);
~i │ │└>0000d17c: f85c83a0 ldur x0, [x29, #-56] <- 0000d178(b)<__vgic_v3_perform_cpuif_access+0x6c>
i │ │ kvm_condition_valid:148.10 (kvm_emulate.h) sbepe return ║kvm_condition_valid32(vcpu);
~i │ │ 0000d180: 940007c4 bl f090 <kvm_condition_valid32>
│ │
i │ │ kvm_condition_valid:148.3 (kvm_emulate.h) sbepe ║return kvm_condition_valid32(vcpu);
~i │ │ 0000d184: 12000008 and w8, w0, #0x1 <- 0000d180(bl-succ)<return>
~i │ │ 0000d188: 381d73a8 sturb w8, [x29, #-41]
~i │┌┼──0000d18c: 14000004 b d19c <__vgic_v3_perform_cpuif_access+0x8c>
│││
~i ││└─>0000d190: 52800028 mov w8, #0x1 // #1 <- 0000d174(b.cc)<__vgic_v3_perform_cpuif_access+0x80>
i ││ kvm_condition_valid:150.2 (kvm_emulate.h) Sbepe ║return true;
~i ││ 0000d194: 381d73a8 sturb w8, [x29, #-41]
~i ││ ┌─0000d198: 14000001 b d19c <__vgic_v3_perform_cpuif_access+0x8c>
││ │
i ││ │ kvm_condition_valid:151.1 (kvm_emulate.h) Sbepe ║}
~i │└>└>0000d19c: 385d73a8 ldurb w8, [x29, #-41] <- 0000d18c(b)<__vgic_v3_perform_cpuif_access+0x8c>,0000d198(b)<__vgic_v3_perform_cpuif_access+0x8c>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd15c 0xd1a0 (DW_OP_fbreg -0x38) kvm_condition_valid(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ __vgic_v3_perform_cpuif_access:985.7 (vgic-v3-sr.c) Sbepe if (║!kvm_condition_valid(vcpu)) {
~ │ ┌──0000d1a0: 370000e8 tbnz w8, #0, d1bc <__vgic_v3_perform_cpuif_access+0xac>
│ │
~ │ │┌─0000d1a4: 14000001 b d1a8 <__vgic_v3_perform_cpuif_access+0x98> <- 0000d1a0(b.cc-succ)<fallthrough>
│ ││
│ ││ __vgic_v3_perform_cpuif_access:986.21 (vgic-v3-sr.c) Sbepe __kvm_skip_instr(║vcpu);
~ │ │└>0000d1a8: f9401be0 ldr x0, [sp, #48] <- 0000d1a4(b)<__vgic_v3_perform_cpuif_access+0x98>
│ │ __vgic_v3_perform_cpuif_access:986.4 (vgic-v3-sr.c) sbepe ║__kvm_skip_instr(vcpu);
~ │ │ 0000d1ac: 94000175 bl d780 <__kvm_skip_instr>
│ │
~ │ │ 0000d1b0: 52800028 mov w8, #0x1 // #1 <- 0000d1ac(bl-succ)<return>
│ │ __vgic_v3_perform_cpuif_access:987.4 (vgic-v3-sr.c) Sbepe ║return 1;
~ │ │ 0000d1b4: b9003fe8 str w8, [sp, #60]
~ ┌───────────────────────────────────┼─┼──0000d1b8: 1400016e b d770 <__vgic_v3_perform_cpuif_access+0x660>
│ │ │
│ │ │ __vgic_v3_perform_cpuif_access:990.12 (vgic-v3-sr.c) Sbepe sysreg = ║esr_cp15_to_sysreg(esr);
~ │ │ └─>0000d1bc: b9402be8 ldr w8, [sp, #40] <- 0000d1a0(b.cc)<__vgic_v3_perform_cpuif_access+0xac>
~ │ │ 0000d1c0: 2a0803e9 mov w9, w8
~ │ │ 0000d1c4: 2a0903e8 mov w8, w9
~ │ │ 0000d1c8: 1216190a and w10, w8, #0x1fc00
~ │ │ 0000d1cc: 530a7d4a lsr w10, w10, #10
~ │ │ 0000d1d0: 121f0d08 and w8, w8, #0x1e
~ │ │ 0000d1d4: 53196108 lsl w8, w8, #7
~ │ │ 0000d1d8: 33141948 bfi w8, w10, #12, #7
~ │ │ 0000d1dc: d3514d29 ubfx x9, x9, #17, #3
~ │ │ 0000d1e0: 331b0928 bfi w8, w9, #5, #3
~ │ │ 0000d1e4: 320d0508 orr w8, w8, #0x180000
~ │ │ 0000d1e8: 2a0803e0 mov w0, w8
│ │ __vgic_v3_perform_cpuif_access:990.10 (vgic-v3-sr.c) sbepe sysreg ║= esr_cp15_to_sysreg(esr);
~ │ │ 0000d1ec: b90013e0 str w0, [sp, #16]
│ │ __vgic_v3_perform_cpuif_access:991.2 (vgic-v3-sr.c) Sbepe ║} else {
~ │ │┌───0000d1f0: 14000013 b d23c <__vgic_v3_perform_cpuif_access+0x12c>
│ ││
│ ││ __vgic_v3_perform_cpuif_access:992.12 (vgic-v3-sr.c) Sbepe sysreg = ║esr_sys64_to_sysreg(esr);
~ │ └┼──>0000d1f4: b9402be8 ldr w8, [sp, #40] <- 0000d14c(b.cc)<__vgic_v3_perform_cpuif_access+0xe4>
~ │ │ 0000d1f8: 2a0803e9 mov w9, w8
~ │ │ 0000d1fc: 2a0903e8 mov w8, w9
~ │ │ 0000d200: d354552a ubfx x10, x9, #20, #2
~ │ │ 0000d204: 1212090b and w11, w8, #0x1c000
~ │ │ 0000d208: 531e756b lsl w11, w11, #2
~ │ │ 0000d20c: 330d054b bfi w11, w10, #19, #2
~ │ │ 0000d210: 12160d0a and w10, w8, #0x3c00
~ │ │ 0000d214: 530a7d4a lsr w10, w10, #10
~ │ │ 0000d218: 33140d4b bfi w11, w10, #12, #4
~ │ │ 0000d21c: 121f0d08 and w8, w8, #0x1e
~ │ │ 0000d220: 53017d08 lsr w8, w8, #1
~ │ │ 0000d224: 33180d0b bfi w11, w8, #8, #4
~ │ │ 0000d228: d3514d29 ubfx x9, x9, #17, #3
~ │ │ 0000d22c: 331b092b bfi w11, w9, #5, #3
~ │ │ 0000d230: 2a0b03e0 mov w0, w11
│ │ __vgic_v3_perform_cpuif_access:992.10 (vgic-v3-sr.c) sbepe sysreg ║= esr_sys64_to_sysreg(esr);
~ │ │ 0000d234: b90013e0 str w0, [sp, #16]
~ │ │ ┌─0000d238: 14000001 b d23c <__vgic_v3_perform_cpuif_access+0x12c>
│ │ │
│ │ │ __vgic_v3_perform_cpuif_access:995.13 (vgic-v3-sr.c) Sbepe is_read = (║esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
~ │ └>└>0000d23c: 3940a3e8 ldrb w8, [sp, #40] <- 0000d1f0(b)<__vgic_v3_perform_cpuif_access+0x12c>,0000d238(b)<__vgic_v3_perform_cpuif_access+0x12c>
│ __vgic_v3_perform_cpuif_access:995.10 (vgic-v3-sr.c) sbepe is_read ║= (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
~ │ 0000d240: 12000108 and w8, w8, #0x1
~ │ 0000d244: 390053e8 strb w8, [sp, #20]
│ __vgic_v3_perform_cpuif_access:997.10 (vgic-v3-sr.c) Sbepe switch (║sysreg) {
~ │ 0000d248: b94013e8 ldr w8, [sp, #16]
│ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ 0000d24c: 2a0803e9 mov w9, w8
~ │ 0000d250: 5288c00a mov w10, #0x4600 // #17920
~ │ 0000d254: 72a0030a movk w10, #0x18, lsl #16
~ │ 0000d258: 6b0a0108 subs w8, w8, w10
~ │ 0000d25c: b9000fe9 str w9, [sp, #12]
~ │ ┌──────────────────────────────0000d260: 540023c0 b.eq d6d8 <__vgic_v3_perform_cpuif_access+0x5c8> // b.none
│ │
~ │ │ ┌─0000d264: 14000001 b d268 <__vgic_v3_perform_cpuif_access+0x158> <- 0000d260(b.cc-succ)<fallthrough>
│ │ │
~ │ │ └>0000d268: 52990008 mov w8, #0xc800 // #51200 <- 0000d264(b)<__vgic_v3_perform_cpuif_access+0x158>
~ │ │ 0000d26c: 72a00308 movk w8, #0x18, lsl #16
~ │ │ 0000d270: b9400fe9 ldr w9, [sp, #12]
│ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ 0000d274: 6b080128 subs w8, w9, w8
~ │ │ ┌──────────0000d278: 54000f40 b.eq d460 <__vgic_v3_perform_cpuif_access+0x350> // b.none
│ │ │
~ │ │ │ ┌─0000d27c: 14000001 b d280 <__vgic_v3_perform_cpuif_access+0x170> <- 0000d278(b.cc-succ)<fallthrough>
│ │ │ │
~ │ │ │ └>0000d280: 52990408 mov w8, #0xc820 // #51232 <- 0000d27c(b)<__vgic_v3_perform_cpuif_access+0x170>
~ │ │ │ 0000d284: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ 0000d288: b9400fe9 ldr w9, [sp, #12]
│ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ 0000d28c: 6b080128 subs w8, w9, w8
~ │ │ ┌─┼──────────0000d290: 54000fc0 b.eq d488 <__vgic_v3_perform_cpuif_access+0x378> // b.none
│ │ │ │
~ │ │ │ │ ┌─0000d294: 14000001 b d298 <__vgic_v3_perform_cpuif_access+0x188> <- 0000d290(b.cc-succ)<fallthrough>
│ │ │ │ │
~ │ │ │ │ └>0000d298: 52990808 mov w8, #0xc840 // #51264 <- 0000d294(b)<__vgic_v3_perform_cpuif_access+0x188>
~ │ │ │ │ 0000d29c: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ 0000d2a0: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ 0000d2a4: 6b080128 subs w8, w9, w8
~ │ │ ┌──────────┼─┼──────────0000d2a8: 54001940 b.eq d5d0 <__vgic_v3_perform_cpuif_access+0x4c0> // b.none
│ │ │ │ │
~ │ │ │ │ │ ┌─0000d2ac: 14000001 b d2b0 <__vgic_v3_perform_cpuif_access+0x1a0> <- 0000d2a8(b.cc-succ)<fallthrough>
│ │ │ │ │ │
~ │ │ │ │ │ └>0000d2b0: 52990c08 mov w8, #0xc860 // #51296 <- 0000d2ac(b)<__vgic_v3_perform_cpuif_access+0x1a0>
~ │ │ │ │ │ 0000d2b4: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ │ 0000d2b8: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ │ 0000d2bc: 6b080128 subs w8, w9, w8
~ │ │ ┌────┼──────────┼─┼──────────0000d2c0: 54001b40 b.eq d628 <__vgic_v3_perform_cpuif_access+0x518> // b.none
│ │ │ │ │ │
~ │ │ │ │ │ │ ┌─0000d2c4: 14000001 b d2c8 <__vgic_v3_perform_cpuif_access+0x1b8> <- 0000d2c0(b.cc-succ)<fallthrough>
│ │ │ │ │ │ │
~ │ │ │ │ │ │ └>0000d2c8: 52991008 mov w8, #0xc880 // #51328 <- 0000d2c4(b)<__vgic_v3_perform_cpuif_access+0x1b8>
~ │ │ │ │ │ │ 0000d2cc: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ │ │ 0000d2d0: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ │ │ 0000d2d4: 6b080128 subs w8, w9, w8
~ │ │ │ │ ┌──┼─┼──────────0000d2d8: 540011c0 b.eq d510 <__vgic_v3_perform_cpuif_access+0x400> // b.none
│ │ │ │ │ │ │
~ │ │ │ │ │ │ │ ┌─0000d2dc: 14000001 b d2e0 <__vgic_v3_perform_cpuif_access+0x1d0> <- 0000d2d8(b.cc-succ)<fallthrough>
│ │ │ │ │ │ │ │
~ │ │ │ │ │ │ │ └>0000d2e0: 52991408 mov w8, #0xc8a0 // #51360 <- 0000d2dc(b)<__vgic_v3_perform_cpuif_access+0x1d0>
~ │ │ │ │ │ │ │ 0000d2e4: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ │ │ │ 0000d2e8: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ │ │ │ 0000d2ec: 6b080128 subs w8, w9, w8
~ │ │ │ │ ┌┼──┼─┼──────────0000d2f0: 54001280 b.eq d540 <__vgic_v3_perform_cpuif_access+0x430> // b.none
│ │ │ │ ││ │ │
~ │ │ │ │ ││ │ │ ┌─0000d2f4: 14000001 b d2f8 <__vgic_v3_perform_cpuif_access+0x1e8> <- 0000d2f0(b.cc-succ)<fallthrough>
│ │ │ │ ││ │ │ │
~ │ │ │ │ ││ │ │ └>0000d2f8: 52991808 mov w8, #0xc8c0 // #51392 <- 0000d2f4(b)<__vgic_v3_perform_cpuif_access+0x1e8>
~ │ │ │ │ ││ │ │ 0000d2fc: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││ │ │ 0000d300: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││ │ │ 0000d304: 6b080128 subs w8, w9, w8
~ │ │ │ │ ┌┼┼──┼─┼──────────0000d308: 54001340 b.eq d570 <__vgic_v3_perform_cpuif_access+0x460> // b.none
│ │ │ │ │││ │ │
~ │ │ │ │ │││ │ │ ┌─0000d30c: 14000001 b d310 <__vgic_v3_perform_cpuif_access+0x200> <- 0000d308(b.cc-succ)<fallthrough>
│ │ │ │ │││ │ │ │
~ │ │ │ │ │││ │ │ └>0000d310: 52991c08 mov w8, #0xc8e0 // #51424 <- 0000d30c(b)<__vgic_v3_perform_cpuif_access+0x200>
~ │ │ │ │ │││ │ │ 0000d314: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ │││ │ │ 0000d318: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ │││ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ │││ │ │ 0000d31c: 6b080128 subs w8, w9, w8
~ │ │ │ │ ┌┼┼┼──┼─┼──────────0000d320: 54001400 b.eq d5a0 <__vgic_v3_perform_cpuif_access+0x490> // b.none
│ │ │ │ ││││ │ │
~ │ │ │ │ ││││ │ │ ┌─0000d324: 14000001 b d328 <__vgic_v3_perform_cpuif_access+0x218> <- 0000d320(b.cc-succ)<fallthrough>
│ │ │ │ ││││ │ │ │
~ │ │ │ │ ││││ │ │ └>0000d328: 52992008 mov w8, #0xc900 // #51456 <- 0000d324(b)<__vgic_v3_perform_cpuif_access+0x218>
~ │ │ │ │ ││││ │ │ 0000d32c: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││││ │ │ 0000d330: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││││ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││││ │ │ 0000d334: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││││ │ │ ┌───────0000d338: 54000ec0 b.eq d510 <__vgic_v3_perform_cpuif_access+0x400> // b.none
│ │ │ │ ││││ │ │ │
~ │ │ │ │ ││││ │ │ │ ┌─0000d33c: 14000001 b d340 <__vgic_v3_perform_cpuif_access+0x230> <- 0000d338(b.cc-succ)<fallthrough>
│ │ │ │ ││││ │ │ │ │
~ │ │ │ │ ││││ │ │ │ └>0000d340: 52992408 mov w8, #0xc920 // #51488 <- 0000d33c(b)<__vgic_v3_perform_cpuif_access+0x230>
~ │ │ │ │ ││││ │ │ │ 0000d344: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││││ │ │ │ 0000d348: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││││ │ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││││ │ │ │ 0000d34c: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││││ │┌┼──┼───────0000d350: 54000f80 b.eq d540 <__vgic_v3_perform_cpuif_access+0x430> // b.none
│ │ │ │ ││││ │││ │
~ │ │ │ │ ││││ │││ │ ┌─0000d354: 14000001 b d358 <__vgic_v3_perform_cpuif_access+0x248> <- 0000d350(b.cc-succ)<fallthrough>
│ │ │ │ ││││ │││ │ │
~ │ │ │ │ ││││ │││ │ └>0000d358: 52992808 mov w8, #0xc940 // #51520 <- 0000d354(b)<__vgic_v3_perform_cpuif_access+0x248>
~ │ │ │ │ ││││ │││ │ 0000d35c: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││││ │││ │ 0000d360: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││││ │││ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││││ │││ │ 0000d364: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││││ ┌┼┼┼──┼───────0000d368: 54001040 b.eq d570 <__vgic_v3_perform_cpuif_access+0x460> // b.none
│ │ │ │ ││││ ││││ │
~ │ │ │ │ ││││ ││││ │ ┌─0000d36c: 14000001 b d370 <__vgic_v3_perform_cpuif_access+0x260> <- 0000d368(b.cc-succ)<fallthrough>
│ │ │ │ ││││ ││││ │ │
~ │ │ │ │ ││││ ││││ │ └>0000d370: 52992c08 mov w8, #0xc960 // #51552 <- 0000d36c(b)<__vgic_v3_perform_cpuif_access+0x260>
~ │ │ │ │ ││││ ││││ │ 0000d374: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││││ ││││ │ 0000d378: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││││ ││││ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││││ ││││ │ 0000d37c: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││││┌┼┼┼┼──┼───────0000d380: 54001100 b.eq d5a0 <__vgic_v3_perform_cpuif_access+0x490> // b.none
│ │ │ │ │││││││││ │
~ │ │ │ │ │││││││││ │ ┌─0000d384: 14000001 b d388 <__vgic_v3_perform_cpuif_access+0x278> <- 0000d380(b.cc-succ)<fallthrough>
│ │ │ │ │││││││││ │ │
~ │ │ │ │ │││││││││ │ └>0000d388: 52996408 mov w8, #0xcb20 // #52000 <- 0000d384(b)<__vgic_v3_perform_cpuif_access+0x278>
~ │ │ │ │ │││││││││ │ 0000d38c: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ │││││││││ │ 0000d390: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ │││││││││ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ │││││││││ │ 0000d394: 6b080128 subs w8, w9, w8
~ │ │ │ ┌┼────┼┼┼┼┼┼┼┼┼──┼───────0000d398: 54001600 b.eq d658 <__vgic_v3_perform_cpuif_access+0x548> // b.none
│ │ │ ││ │││││││││ │
~ │ │ │ ││ │││││││││ │ ┌─0000d39c: 14000001 b d3a0 <__vgic_v3_perform_cpuif_access+0x290> <- 0000d398(b.cc-succ)<fallthrough>
│ │ │ ││ │││││││││ │ │
~ │ │ │ ││ │││││││││ │ └>0000d3a0: 52996c08 mov w8, #0xcb60 // #52064 <- 0000d39c(b)<__vgic_v3_perform_cpuif_access+0x290>
~ │ │ │ ││ │││││││││ │ 0000d3a4: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ ││ │││││││││ │ 0000d3a8: b9400fe9 ldr w9, [sp, #12]
│ │ │ ││ │││││││││ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ ││ │││││││││ │ 0000d3ac: 6b080128 subs w8, w9, w8
~ │ │ │ ┌─┼┼────┼┼┼┼┼┼┼┼┼──┼───────0000d3b0: 54001680 b.eq d680 <__vgic_v3_perform_cpuif_access+0x570> // b.none
│ │ │ │ ││ │││││││││ │
~ │ │ │ │ ││ │││││││││ │ ┌─0000d3b4: 14000001 b d3b8 <__vgic_v3_perform_cpuif_access+0x2a8> <- 0000d3b0(b.cc-succ)<fallthrough>
│ │ │ │ ││ │││││││││ │ │
~ │ │ │ │ ││ │││││││││ │ └>0000d3b8: 52998008 mov w8, #0xcc00 // #52224 <- 0000d3b4(b)<__vgic_v3_perform_cpuif_access+0x2a8>
~ │ │ │ │ ││ │││││││││ │ 0000d3bc: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││ │││││││││ │ 0000d3c0: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││ │││││││││ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││ │││││││││ │ 0000d3c4: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││ │││││││││ │ ┌──0000d3c8: 540004c0 b.eq d460 <__vgic_v3_perform_cpuif_access+0x350> // b.none
│ │ │ │ ││ │││││││││ │ │
~ │ │ │ │ ││ │││││││││ │ │┌─0000d3cc: 14000001 b d3d0 <__vgic_v3_perform_cpuif_access+0x2c0> <- 0000d3c8(b.cc-succ)<fallthrough>
│ │ │ │ ││ │││││││││ │ ││
~ │ │ │ │ ││ │││││││││ │ │└>0000d3d0: 52998408 mov w8, #0xcc20 // #52256 <- 0000d3cc(b)<__vgic_v3_perform_cpuif_access+0x2c0>
~ │ │ │ │ ││ │││││││││ │ │ 0000d3d4: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││ │││││││││ │ │ 0000d3d8: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││ │││││││││ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││ │││││││││ │ │ 0000d3dc: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││ │││││││││ │ ┌─┼──0000d3e0: 54000540 b.eq d488 <__vgic_v3_perform_cpuif_access+0x378> // b.none
│ │ │ │ ││ │││││││││ │ │ │
~ │ │ │ │ ││ │││││││││ │ │ │┌─0000d3e4: 14000001 b d3e8 <__vgic_v3_perform_cpuif_access+0x2d8> <- 0000d3e0(b.cc-succ)<fallthrough>
│ │ │ │ ││ │││││││││ │ │ ││
~ │ │ │ │ ││ │││││││││ │ │ │└>0000d3e8: 52998808 mov w8, #0xcc40 // #52288 <- 0000d3e4(b)<__vgic_v3_perform_cpuif_access+0x2d8>
~ │ │ │ │ ││ │││││││││ │ │ │ 0000d3ec: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││ │││││││││ │ │ │ 0000d3f0: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││ │││││││││ │ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││ │││││││││ │ │ │ 0000d3f4: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││ │││││││││ ┌┼──┼─┼──0000d3f8: 54000ec0 b.eq d5d0 <__vgic_v3_perform_cpuif_access+0x4c0> // b.none
│ │ │ │ ││ │││││││││ ││ │ │
~ │ │ │ │ ││ │││││││││ ││ │ │┌─0000d3fc: 14000001 b d400 <__vgic_v3_perform_cpuif_access+0x2f0> <- 0000d3f8(b.cc-succ)<fallthrough>
│ │ │ │ ││ │││││││││ ││ │ ││
~ │ │ │ │ ││ │││││││││ ││ │ │└>0000d400: 52998c08 mov w8, #0xcc60 // #52320 <- 0000d3fc(b)<__vgic_v3_perform_cpuif_access+0x2f0>
~ │ │ │ │ ││ │││││││││ ││ │ │ 0000d404: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││ │││││││││ ││ │ │ 0000d408: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││ │││││││││ ││ │ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││ │││││││││ ││ │ │ 0000d40c: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││ │││││││││ ││ ┌┼─┼──0000d410: 54000680 b.eq d4e0 <__vgic_v3_perform_cpuif_access+0x3d0> // b.none
│ │ │ │ ││ │││││││││ ││ ││ │
~ │ │ │ │ ││ │││││││││ ││ ││ │┌─0000d414: 14000001 b d418 <__vgic_v3_perform_cpuif_access+0x308> <- 0000d410(b.cc-succ)<fallthrough>
│ │ │ │ ││ │││││││││ ││ ││ ││
~ │ │ │ │ ││ │││││││││ ││ ││ │└>0000d418: 52999008 mov w8, #0xcc80 // #52352 <- 0000d414(b)<__vgic_v3_perform_cpuif_access+0x308>
~ │ │ │ │ ││ │││││││││ ││ ││ │ 0000d41c: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││ │││││││││ ││ ││ │ 0000d420: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││ │││││││││ ││ ││ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││ │││││││││ ││ ││ │ 0000d424: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││ ┌┼┼┼┼┼┼┼┼┼─┼┼─┼┼─┼──0000d428: 54001400 b.eq d6a8 <__vgic_v3_perform_cpuif_access+0x598> // b.none
│ │ │ │ ││ ││││││││││ ││ ││ │
~ │ │ │ │ ││ ││││││││││ ││ ││ │┌─0000d42c: 14000001 b d430 <__vgic_v3_perform_cpuif_access+0x320> <- 0000d428(b.cc-succ)<fallthrough>
│ │ │ │ ││ ││││││││││ ││ ││ ││
~ │ │ │ │ ││ ││││││││││ ││ ││ │└>0000d430: 52999808 mov w8, #0xccc0 // #52416 <- 0000d42c(b)<__vgic_v3_perform_cpuif_access+0x320>
~ │ │ │ │ ││ ││││││││││ ││ ││ │ 0000d434: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││ ││││││││││ ││ ││ │ 0000d438: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││ ││││││││││ ││ ││ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││ ││││││││││ ││ ││ │ 0000d43c: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││ ││││││││││ ││┌┼┼─┼──0000d440: 54000dc0 b.eq d5f8 <__vgic_v3_perform_cpuif_access+0x4e8> // b.none
│ │ │ │ ││ ││││││││││ │││││ │
~ │ │ │ │ ││ ││││││││││ │││││ │┌─0000d444: 14000001 b d448 <__vgic_v3_perform_cpuif_access+0x338> <- 0000d440(b.cc-succ)<fallthrough>
│ │ │ │ ││ ││││││││││ │││││ ││
~ │ │ │ │ ││ ││││││││││ │││││ │└>0000d448: 52999c08 mov w8, #0xcce0 // #52448 <- 0000d444(b)<__vgic_v3_perform_cpuif_access+0x338>
~ │ │ │ │ ││ ││││││││││ │││││ │ 0000d44c: 72a00308 movk w8, #0x18, lsl #16
~ │ │ │ │ ││ ││││││││││ │││││ │ 0000d450: b9400fe9 ldr w9, [sp, #12]
│ │ │ │ ││ ││││││││││ │││││ │ __vgic_v3_perform_cpuif_access:997.2 (vgic-v3-sr.c) sbepe ║switch (sysreg) {
~ │ │ │ │ ││ ││││││││││ │││││ │ 0000d454: 6b080128 subs w8, w9, w8
~ │ │ │ │ ││ ││││││││││ │││││┌┼──0000d458: 540002c0 b.eq d4b0 <__vgic_v3_perform_cpuif_access+0x3a0> // b.none
│ │ │ │ ││ ││││││││││ │││││││
~ │ │ │ │ ││ ┌─┼┼┼┼┼┼┼┼┼┼─┼┼┼┼┼┼┼──0000d45c: 140000ab b d708 <__vgic_v3_perform_cpuif_access+0x5f8> <- 0000d458(b.cc-succ)<fallthrough>
│ │ │ │ ││ │ ││││││││││ │││││││
│ │ │ │ ││ │ ││││││││││ │││││││ __vgic_v3_perform_cpuif_access:1000.7 (vgic-v3-sr.c) Sbepe if (║unlikely(!is_read))
~ │ │ │ │ ││ │ │││││││││└>││││││└─>0000d460: 394053e8 ldrb w8, [sp, #20] <- 0000d278(b.cc)<__vgic_v3_perform_cpuif_access+0x350>,0000d3c8(b.cc)<__vgic_v3_perform_cpuif_access+0x350>
│ │ │ │ ││ │ │││││││││ ││││││ __vgic_v3_perform_cpuif_access:1000.7 (vgic-v3-sr.c) sbepe if (║unlikely(!is_read))
~ │ │ │ │ ││ │ │││││││││ ││││││┌──0000d464: 370000a8 tbnz w8, #0, d478 <__vgic_v3_perform_cpuif_access+0x368>
│ │ │ │ ││ │ │││││││││ │││││││
~ │ │ │ │ ││ │ │││││││││ │││││││┌─0000d468: 14000001 b d46c <__vgic_v3_perform_cpuif_access+0x35c> <- 0000d464(b.cc-succ)<fallthrough>
│ │ │ │ ││ │ │││││││││ ││││││││
~ │ │ │ │ ││ │ │││││││││ │││││││└>0000d46c: 2a1f03e8 mov w8, wzr <- 0000d468(b)<__vgic_v3_perform_cpuif_access+0x35c>
│ │ │ │ ││ │ │││││││││ │││││││ __vgic_v3_perform_cpuif_access:1001.4 (vgic-v3-sr.c) Sbepe ║return 0;
~ │ │ │ │ ││ │ │││││││││ │││││││ 0000d470: b9003fe8 str w8, [sp, #60]
~ │ ┌───────┼─┼─┼─┼┼─┼─┼┼┼┼┼┼┼┼┼──┼┼┼┼┼┼┼──0000d474: 140000bf b d770 <__vgic_v3_perform_cpuif_access+0x660>
│ │ │ │ │ ││ │ │││││││││ │││││││
│ │ │ │ │ ││ │ │││││││││ │││││││ __vgic_v3_perform_cpuif_access:1002.6 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_iar;
~ │ │ │ │ │ ││ │ │││││││││ ││││││└─>0000d478: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d464(b.cc)<__vgic_v3_perform_cpuif_access+0x368>
~ │ │ │ │ │ ││ │ │││││││││ ││││││ 0000d47c: 91209108 add x8, x8, #0x824
~ │ │ │ │ │ ││ │ │││││││││ ││││││ 0000d480: f9000fe8 str x8, [sp, #24]
│ │ │ │ │ ││ │ │││││││││ ││││││ __vgic_v3_perform_cpuif_access:1003.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ┌────┼─┼─┼─┼┼─┼─┼┼┼┼┼┼┼┼┼──┼┼┼┼┼┼───0000d484: 140000a4 b d714 <__vgic_v3_perform_cpuif_access+0x604>
│ │ │ │ │ │ ││ │ │││││││││ ││││││
│ │ │ │ │ │ ││ │ │││││││││ ││││││ __vgic_v3_perform_cpuif_access:1006.7 (vgic-v3-sr.c) Sbepe if (║unlikely(is_read))
~ │ │ │ │ │ │ ││ │ │││││││└┼─>││││└┼──>0000d488: 394053e8 ldrb w8, [sp, #20] <- 0000d290(b.cc)<__vgic_v3_perform_cpuif_access+0x378>,0000d3e0(b.cc)<__vgic_v3_perform_cpuif_access+0x378>
│ │ │ │ │ │ ││ │ │││││││ │ ││││ │ __vgic_v3_perform_cpuif_access:1006.7 (vgic-v3-sr.c) sbepe if (║unlikely(is_read))
~ │ │ │ │ │ │ ││ │ │││││││ │ ││││ │┌──0000d48c: 360000a8 tbz w8, #0, d4a0 <__vgic_v3_perform_cpuif_access+0x390>
│ │ │ │ │ │ ││ │ │││││││ │ ││││ ││
~ │ │ │ │ │ │ ││ │ │││││││ │ ││││ ││┌─0000d490: 14000001 b d494 <__vgic_v3_perform_cpuif_access+0x384> <- 0000d48c(b.cc-succ)<fallthrough>
│ │ │ │ │ │ ││ │ │││││││ │ ││││ │││
~ │ │ │ │ │ │ ││ │ │││││││ │ ││││ ││└>0000d494: 2a1f03e8 mov w8, wzr <- 0000d490(b)<__vgic_v3_perform_cpuif_access+0x384>
│ │ │ │ │ │ ││ │ │││││││ │ ││││ ││ __vgic_v3_perform_cpuif_access:1007.4 (vgic-v3-sr.c) Sbepe ║return 0;
~ │ │ │ │ │ │ ││ │ │││││││ │ ││││ ││ 0000d498: b9003fe8 str w8, [sp, #60]
~ │ │ ┌┼────┼─┼─┼─┼┼─┼─┼┼┼┼┼┼┼─┼──┼┼┼┼─┼┼──0000d49c: 140000b5 b d770 <__vgic_v3_perform_cpuif_access+0x660>
│ │ ││ │ │ │ ││ │ │││││││ │ ││││ ││
│ │ ││ │ │ │ ││ │ │││││││ │ ││││ ││ __vgic_v3_perform_cpuif_access:1008.6 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_eoir;
~ │ │ ││ │ │ │ ││ │ │││││││ │ ││││ │└─>0000d4a0: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d48c(b.cc)<__vgic_v3_perform_cpuif_access+0x390>
~ │ │ ││ │ │ │ ││ │ │││││││ │ ││││ │ 0000d4a4: 91276108 add x8, x8, #0x9d8
~ │ │ ││ │ │ │ ││ │ │││││││ │ ││││ │ 0000d4a8: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │ │ ││ │ │││││││ │ ││││ │ __vgic_v3_perform_cpuif_access:1009.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ ┌──┼─┼─┼─┼┼─┼─┼┼┼┼┼┼┼─┼──┼┼┼┼─┼───0000d4ac: 1400009a b d714 <__vgic_v3_perform_cpuif_access+0x604>
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │ __vgic_v3_perform_cpuif_access:1011.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ └──>0000d4b0: 394053e8 ldrb w8, [sp, #20] <- 0000d458(b.cc)<__vgic_v3_perform_cpuif_access+0x3a0>
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ __vgic_v3_perform_cpuif_access:1011.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ ┌──0000d4b4: 360000c8 tbz w8, #0, d4cc <__vgic_v3_perform_cpuif_access+0x3bc>
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │┌─0000d4b8: 14000001 b d4bc <__vgic_v3_perform_cpuif_access+0x3ac> <- 0000d4b4(b.cc-succ)<fallthrough>
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ ││
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ ││ __vgic_v3_perform_cpuif_access:1012.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_igrpen1;
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │└>0000d4bc: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d4b8(b)<__vgic_v3_perform_cpuif_access+0x3ac>
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │ 0000d4c0: 912c2108 add x8, x8, #0xb08
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │ 0000d4c4: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │ __vgic_v3_perform_cpuif_access:1012.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_igrpen1;
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ ┌┼──0000d4c8: 14000005 b d4dc <__vgic_v3_perform_cpuif_access+0x3cc>
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ ││
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ ││ __vgic_v3_perform_cpuif_access:1014.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_igrpen1;
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │└─>0000d4cc: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d4b4(b.cc)<__vgic_v3_perform_cpuif_access+0x3bc>
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │ 0000d4d0: 912db108 add x8, x8, #0xb6c
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │ 0000d4d4: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │ ┌─0000d4d8: 14000001 b d4dc <__vgic_v3_perform_cpuif_access+0x3cc>
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │ │
│ │ ││ │ │ │ │ ││ │ │││││││ │ ││││ │ │ __vgic_v3_perform_cpuif_access:1015.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ ┌┼─┼─┼─┼┼─┼─┼┼┼┼┼┼┼─┼──┼┼┼┼─└>└>0000d4dc: 1400008e b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d4c8(b)<__vgic_v3_perform_cpuif_access+0x3cc>,0000d4d8(b)<__vgic_v3_perform_cpuif_access+0x3cc>
│ │ ││ │ ││ │ │ ││ │ │││││││ │ ││││
│ │ ││ │ ││ │ │ ││ │ │││││││ │ ││││ __vgic_v3_perform_cpuif_access:1017.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││└────>0000d4e0: 394053e8 ldrb w8, [sp, #20] <- 0000d410(b.cc)<__vgic_v3_perform_cpuif_access+0x3d0>
│ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ __vgic_v3_perform_cpuif_access:1017.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ ┌──0000d4e4: 360000c8 tbz w8, #0, d4fc <__vgic_v3_perform_cpuif_access+0x3ec>
│ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │┌─0000d4e8: 14000001 b d4ec <__vgic_v3_perform_cpuif_access+0x3dc> <- 0000d4e4(b.cc-succ)<fallthrough>
│ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ ││
│ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ ││ __vgic_v3_perform_cpuif_access:1018.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_bpr1;
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │└>0000d4ec: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d4e8(b)<__vgic_v3_perform_cpuif_access+0x3dc>
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │ 0000d4f0: 91305108 add x8, x8, #0xc14
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │ 0000d4f4: f9000fe8 str x8, [sp, #24]
│ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │ __vgic_v3_perform_cpuif_access:1018.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_bpr1;
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ ┌┼──0000d4f8: 14000005 b d50c <__vgic_v3_perform_cpuif_access+0x3fc>
│ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ ││
│ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ ││ __vgic_v3_perform_cpuif_access:1020.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_bpr1;
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │└─>0000d4fc: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d4e4(b.cc)<__vgic_v3_perform_cpuif_access+0x3ec>
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │ 0000d500: 91326108 add x8, x8, #0xc98
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │ 0000d504: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │ ┌─0000d508: 14000001 b d50c <__vgic_v3_perform_cpuif_access+0x3fc>
│ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │ │
│ │ ││ │ ││ │ │ ││ │ │││││││ │ │││ │ │ __vgic_v3_perform_cpuif_access:1021.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ ││┌┼─┼─┼┼─┼─┼┼┼┼┼┼┼─┼──┼┼┼──└>└>0000d50c: 14000082 b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d4f8(b)<__vgic_v3_perform_cpuif_access+0x3fc>,0000d508(b)<__vgic_v3_perform_cpuif_access+0x3fc>
│ │ ││ │ ││││ │ ││ │ │││││││ │ │││
│ │ ││ │ ││││ │ ││ │ │││││││ │ │││ __vgic_v3_perform_cpuif_access:1024.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ ││││ │ ││ │ ││││└┼┼─┼─>│└┼─────>0000d510: 394053e8 ldrb w8, [sp, #20] <- 0000d2d8(b.cc)<__vgic_v3_perform_cpuif_access+0x400>,0000d338(b.cc)<__vgic_v3_perform_cpuif_access+0x400>
│ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ __vgic_v3_perform_cpuif_access:1024.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ ┌──0000d514: 360000c8 tbz w8, #0, d52c <__vgic_v3_perform_cpuif_access+0x41c>
│ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │┌─0000d518: 14000001 b d51c <__vgic_v3_perform_cpuif_access+0x40c> <- 0000d514(b.cc-succ)<fallthrough>
│ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ ││
│ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ ││ __vgic_v3_perform_cpuif_access:1025.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_apxr0;
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │└>0000d51c: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d518(b)<__vgic_v3_perform_cpuif_access+0x40c>
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │ 0000d520: 91364108 add x8, x8, #0xd90
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │ 0000d524: f9000fe8 str x8, [sp, #24]
│ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │ __vgic_v3_perform_cpuif_access:1025.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_apxr0;
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ ┌┼──0000d528: 14000005 b d53c <__vgic_v3_perform_cpuif_access+0x42c>
│ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ ││
│ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ ││ __vgic_v3_perform_cpuif_access:1027.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_apxr0;
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │└─>0000d52c: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d514(b.cc)<__vgic_v3_perform_cpuif_access+0x41c>
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │ 0000d530: 91371108 add x8, x8, #0xdc4
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │ 0000d534: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │ ┌─0000d538: 14000001 b d53c <__vgic_v3_perform_cpuif_access+0x42c>
│ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │ │
│ │ ││ │ ││││ │ ││ │ ││││ ││ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1028.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ ││││┌┼─┼┼─┼─┼┼┼┼─┼┼─┼──┼─┼──└>└>0000d53c: 14000076 b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d528(b)<__vgic_v3_perform_cpuif_access+0x42c>,0000d538(b)<__vgic_v3_perform_cpuif_access+0x42c>
│ │ ││ │ ││││││ ││ │ ││││ ││ │ │ │
│ │ ││ │ ││││││ ││ │ ││││ ││ │ │ │ __vgic_v3_perform_cpuif_access:1031.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ ││││││ ││ │ │││└─┼┼>└──┼─┼─────>0000d540: 394053e8 ldrb w8, [sp, #20] <- 0000d2f0(b.cc)<__vgic_v3_perform_cpuif_access+0x430>,0000d350(b.cc)<__vgic_v3_perform_cpuif_access+0x430>
│ │ ││ │ ││││││ ││ │ │││ ││ │ │ __vgic_v3_perform_cpuif_access:1031.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ ┌──0000d544: 360000c8 tbz w8, #0, d55c <__vgic_v3_perform_cpuif_access+0x44c>
│ │ ││ │ ││││││ ││ │ │││ ││ │ │ │
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ │┌─0000d548: 14000001 b d54c <__vgic_v3_perform_cpuif_access+0x43c> <- 0000d544(b.cc-succ)<fallthrough>
│ │ ││ │ ││││││ ││ │ │││ ││ │ │ ││
│ │ ││ │ ││││││ ││ │ │││ ││ │ │ ││ __vgic_v3_perform_cpuif_access:1032.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_apxr1;
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ │└>0000d54c: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d548(b)<__vgic_v3_perform_cpuif_access+0x43c>
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ │ 0000d550: 9137e108 add x8, x8, #0xdf8
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ │ 0000d554: f9000fe8 str x8, [sp, #24]
│ │ ││ │ ││││││ ││ │ │││ ││ │ │ │ __vgic_v3_perform_cpuif_access:1032.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_apxr1;
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ ┌┼──0000d558: 14000005 b d56c <__vgic_v3_perform_cpuif_access+0x45c>
│ │ ││ │ ││││││ ││ │ │││ ││ │ │ ││
│ │ ││ │ ││││││ ││ │ │││ ││ │ │ ││ __vgic_v3_perform_cpuif_access:1034.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_apxr1;
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ │└─>0000d55c: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d544(b.cc)<__vgic_v3_perform_cpuif_access+0x44c>
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ │ 0000d560: 9138b108 add x8, x8, #0xe2c
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ │ 0000d564: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ ││││││ ││ │ │││ ││ │ │ │ ┌─0000d568: 14000001 b d56c <__vgic_v3_perform_cpuif_access+0x45c>
│ │ ││ │ ││││││ ││ │ │││ ││ │ │ │ │
│ │ ││ │ ││││││ ││ │ │││ ││ │ │ │ │ __vgic_v3_perform_cpuif_access:1035.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ ││││││┌┼┼─┼─┼┼┼──┼┼────┼─┼──└>└>0000d56c: 1400006a b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d558(b)<__vgic_v3_perform_cpuif_access+0x45c>,0000d568(b)<__vgic_v3_perform_cpuif_access+0x45c>
│ │ ││ │ │││││││││ │ │││ ││ │ │
│ │ ││ │ │││││││││ │ │││ ││ │ │ __vgic_v3_perform_cpuif_access:1038.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ │││││││││ │ ││└─>│└────┼─┼─────>0000d570: 394053e8 ldrb w8, [sp, #20] <- 0000d308(b.cc)<__vgic_v3_perform_cpuif_access+0x460>,0000d368(b.cc)<__vgic_v3_perform_cpuif_access+0x460>
│ │ ││ │ │││││││││ │ ││ │ │ │ __vgic_v3_perform_cpuif_access:1038.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ │││││││││ │ ││ │ │ │ ┌──0000d574: 360000c8 tbz w8, #0, d58c <__vgic_v3_perform_cpuif_access+0x47c>
│ │ ││ │ │││││││││ │ ││ │ │ │ │
~ │ │ ││ │ │││││││││ │ ││ │ │ │ │┌─0000d578: 14000001 b d57c <__vgic_v3_perform_cpuif_access+0x46c> <- 0000d574(b.cc-succ)<fallthrough>
│ │ ││ │ │││││││││ │ ││ │ │ │ ││
│ │ ││ │ │││││││││ │ ││ │ │ │ ││ __vgic_v3_perform_cpuif_access:1039.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_apxr2;
~ │ │ ││ │ │││││││││ │ ││ │ │ │ │└>0000d57c: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d578(b)<__vgic_v3_perform_cpuif_access+0x46c>
~ │ │ ││ │ │││││││││ │ ││ │ │ │ │ 0000d580: 91398108 add x8, x8, #0xe60
~ │ │ ││ │ │││││││││ │ ││ │ │ │ │ 0000d584: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │││││││││ │ ││ │ │ │ │ __vgic_v3_perform_cpuif_access:1039.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_apxr2;
~ │ │ ││ │ │││││││││ │ ││ │ │ │ ┌┼──0000d588: 14000005 b d59c <__vgic_v3_perform_cpuif_access+0x48c>
│ │ ││ │ │││││││││ │ ││ │ │ │ ││
│ │ ││ │ │││││││││ │ ││ │ │ │ ││ __vgic_v3_perform_cpuif_access:1041.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_apxr2;
~ │ │ ││ │ │││││││││ │ ││ │ │ │ │└─>0000d58c: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d574(b.cc)<__vgic_v3_perform_cpuif_access+0x47c>
~ │ │ ││ │ │││││││││ │ ││ │ │ │ │ 0000d590: 913a5108 add x8, x8, #0xe94
~ │ │ ││ │ │││││││││ │ ││ │ │ │ │ 0000d594: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ │││││││││ │ ││ │ │ │ │ ┌─0000d598: 14000001 b d59c <__vgic_v3_perform_cpuif_access+0x48c>
│ │ ││ │ │││││││││ │ ││ │ │ │ │ │
│ │ ││ │ │││││││││ │ ││ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1042.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ │││││││││┌┼─┼┼───┼─────┼─┼──└>└>0000d59c: 1400005e b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d588(b)<__vgic_v3_perform_cpuif_access+0x48c>,0000d598(b)<__vgic_v3_perform_cpuif_access+0x48c>
│ │ ││ │ │││││││││││ ││ │ │ │
│ │ ││ │ │││││││││││ ││ │ │ │ __vgic_v3_perform_cpuif_access:1045.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ │││││││││││ │└──>└─────┼─┼─────>0000d5a0: 394053e8 ldrb w8, [sp, #20] <- 0000d320(b.cc)<__vgic_v3_perform_cpuif_access+0x490>,0000d380(b.cc)<__vgic_v3_perform_cpuif_access+0x490>
│ │ ││ │ │││││││││││ │ │ │ __vgic_v3_perform_cpuif_access:1045.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ │││││││││││ │ │ │ ┌──0000d5a4: 360000c8 tbz w8, #0, d5bc <__vgic_v3_perform_cpuif_access+0x4ac>
│ │ ││ │ │││││││││││ │ │ │ │
~ │ │ ││ │ │││││││││││ │ │ │ │┌─0000d5a8: 14000001 b d5ac <__vgic_v3_perform_cpuif_access+0x49c> <- 0000d5a4(b.cc-succ)<fallthrough>
│ │ ││ │ │││││││││││ │ │ │ ││
│ │ ││ │ │││││││││││ │ │ │ ││ __vgic_v3_perform_cpuif_access:1046.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_apxr3;
~ │ │ ││ │ │││││││││││ │ │ │ │└>0000d5ac: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d5a8(b)<__vgic_v3_perform_cpuif_access+0x49c>
~ │ │ ││ │ │││││││││││ │ │ │ │ 0000d5b0: 913b2108 add x8, x8, #0xec8
~ │ │ ││ │ │││││││││││ │ │ │ │ 0000d5b4: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │││││││││││ │ │ │ │ __vgic_v3_perform_cpuif_access:1046.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_apxr3;
~ │ │ ││ │ │││││││││││ │ │ │ ┌┼──0000d5b8: 14000005 b d5cc <__vgic_v3_perform_cpuif_access+0x4bc>
│ │ ││ │ │││││││││││ │ │ │ ││
│ │ ││ │ │││││││││││ │ │ │ ││ __vgic_v3_perform_cpuif_access:1048.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_apxr3;
~ │ │ ││ │ │││││││││││ │ │ │ │└─>0000d5bc: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d5a4(b.cc)<__vgic_v3_perform_cpuif_access+0x4ac>
~ │ │ ││ │ │││││││││││ │ │ │ │ 0000d5c0: 913bf108 add x8, x8, #0xefc
~ │ │ ││ │ │││││││││││ │ │ │ │ 0000d5c4: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ │││││││││││ │ │ │ │ ┌─0000d5c8: 14000001 b d5cc <__vgic_v3_perform_cpuif_access+0x4bc>
│ │ ││ │ │││││││││││ │ │ │ │ │
│ │ ││ │ │││││││││││ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1049.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ │││││││││││┌┼──────────┼─┼──└>└>0000d5cc: 14000052 b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d5b8(b)<__vgic_v3_perform_cpuif_access+0x4bc>,0000d5c8(b)<__vgic_v3_perform_cpuif_access+0x4bc>
│ │ ││ │ │││││││││││││ │ │
│ │ ││ │ │││││││││││││ │ │ __vgic_v3_perform_cpuif_access:1052.7 (vgic-v3-sr.c) Sbepe if (║unlikely(!is_read))
~ │ │ ││ │ ││││││││└┼┼┼┼─────────>└─┼─────>0000d5d0: 394053e8 ldrb w8, [sp, #20] <- 0000d2a8(b.cc)<__vgic_v3_perform_cpuif_access+0x4c0>,0000d3f8(b.cc)<__vgic_v3_perform_cpuif_access+0x4c0>
│ │ ││ │ ││││││││ ││││ │ __vgic_v3_perform_cpuif_access:1052.7 (vgic-v3-sr.c) sbepe if (║unlikely(!is_read))
~ │ │ ││ │ ││││││││ ││││ │ ┌──0000d5d4: 370000a8 tbnz w8, #0, d5e8 <__vgic_v3_perform_cpuif_access+0x4d8>
│ │ ││ │ ││││││││ ││││ │ │
~ │ │ ││ │ ││││││││ ││││ │ │┌─0000d5d8: 14000001 b d5dc <__vgic_v3_perform_cpuif_access+0x4cc> <- 0000d5d4(b.cc-succ)<fallthrough>
│ │ ││ │ ││││││││ ││││ │ ││
~ │ │ ││ │ ││││││││ ││││ │ │└>0000d5dc: 2a1f03e8 mov w8, wzr <- 0000d5d8(b)<__vgic_v3_perform_cpuif_access+0x4cc>
│ │ ││ │ ││││││││ ││││ │ │ __vgic_v3_perform_cpuif_access:1053.4 (vgic-v3-sr.c) Sbepe ║return 0;
~ │ │ ││ │ ││││││││ ││││ │ │ 0000d5e0: b9003fe8 str w8, [sp, #60]
~ │ │ ││ │ ││││││││┌┼┼┼┼────────────┼───┼──0000d5e4: 14000063 b d770 <__vgic_v3_perform_cpuif_access+0x660>
│ │ ││ │ │││││││││││││ │ │
│ │ ││ │ │││││││││││││ │ │ __vgic_v3_perform_cpuif_access:1054.6 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_hppir;
~ │ │ ││ │ │││││││││││││ │ └─>0000d5e8: 90000008 adrp x8, d000 <__vgic_v3_write_ap1rn+0x98> <- 0000d5d4(b.cc)<__vgic_v3_perform_cpuif_access+0x4d8>
~ │ │ ││ │ │││││││││││││ │ 0000d5ec: 913cc108 add x8, x8, #0xf30
~ │ │ ││ │ │││││││││││││ │ 0000d5f0: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │││││││││││││ │ __vgic_v3_perform_cpuif_access:1055.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ │││││││││││││┌───────────┼──────0000d5f4: 14000048 b d714 <__vgic_v3_perform_cpuif_access+0x604>
│ │ ││ │ ││││││││││││││ │
│ │ ││ │ ││││││││││││││ │ __vgic_v3_perform_cpuif_access:1057.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ ││││││││││││││ └─────>0000d5f8: 394053e8 ldrb w8, [sp, #20] <- 0000d440(b.cc)<__vgic_v3_perform_cpuif_access+0x4e8>
│ │ ││ │ ││││││││││││││ __vgic_v3_perform_cpuif_access:1057.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ ││││││││││││││ ┌──0000d5fc: 360000c8 tbz w8, #0, d614 <__vgic_v3_perform_cpuif_access+0x504>
│ │ ││ │ ││││││││││││││ │
~ │ │ ││ │ ││││││││││││││ │┌─0000d600: 14000001 b d604 <__vgic_v3_perform_cpuif_access+0x4f4> <- 0000d5fc(b.cc-succ)<fallthrough>
│ │ ││ │ ││││││││││││││ ││
│ │ ││ │ ││││││││││││││ ││ __vgic_v3_perform_cpuif_access:1058.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_igrpen0;
~ │ │ ││ │ ││││││││││││││ │└>0000d604: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d600(b)<__vgic_v3_perform_cpuif_access+0x4f4>
~ │ │ ││ │ ││││││││││││││ │ 0000d608: 91001108 add x8, x8, #0x4
~ │ │ ││ │ ││││││││││││││ │ 0000d60c: f9000fe8 str x8, [sp, #24]
│ │ ││ │ ││││││││││││││ │ __vgic_v3_perform_cpuif_access:1058.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_igrpen0;
~ │ │ ││ │ ││││││││││││││ ┌┼──0000d610: 14000005 b d624 <__vgic_v3_perform_cpuif_access+0x514>
│ │ ││ │ ││││││││││││││ ││
│ │ ││ │ ││││││││││││││ ││ __vgic_v3_perform_cpuif_access:1060.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_igrpen0;
~ │ │ ││ │ ││││││││││││││ │└─>0000d614: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d5fc(b.cc)<__vgic_v3_perform_cpuif_access+0x504>
~ │ │ ││ │ ││││││││││││││ │ 0000d618: 9101a108 add x8, x8, #0x68
~ │ │ ││ │ ││││││││││││││ │ 0000d61c: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ ││││││││││││││ │ ┌─0000d620: 14000001 b d624 <__vgic_v3_perform_cpuif_access+0x514>
│ │ ││ │ ││││││││││││││ │ │
│ │ ││ │ ││││││││││││││ │ │ __vgic_v3_perform_cpuif_access:1061.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ ││││││││││││││ ┌───────────└>└>0000d624: 1400003c b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d610(b)<__vgic_v3_perform_cpuif_access+0x514>,0000d620(b)<__vgic_v3_perform_cpuif_access+0x514>
│ │ ││ │ ││││││││││││││ │
│ │ ││ │ ││││││││││││││ │ __vgic_v3_perform_cpuif_access:1063.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ │││└┼┼┼┼┼┼┼┼┼┼──┼──────────────>0000d628: 394053e8 ldrb w8, [sp, #20] <- 0000d2c0(b.cc)<__vgic_v3_perform_cpuif_access+0x518>
│ │ ││ │ │││ ││││││││││ │ __vgic_v3_perform_cpuif_access:1063.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ │││ ││││││││││ │ ┌──0000d62c: 360000c8 tbz w8, #0, d644 <__vgic_v3_perform_cpuif_access+0x534>
│ │ ││ │ │││ ││││││││││ │ │
~ │ │ ││ │ │││ ││││││││││ │ │┌─0000d630: 14000001 b d634 <__vgic_v3_perform_cpuif_access+0x524> <- 0000d62c(b.cc-succ)<fallthrough>
│ │ ││ │ │││ ││││││││││ │ ││
│ │ ││ │ │││ ││││││││││ │ ││ __vgic_v3_perform_cpuif_access:1064.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_bpr0;
~ │ │ ││ │ │││ ││││││││││ │ │└>0000d634: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d630(b)<__vgic_v3_perform_cpuif_access+0x524>
~ │ │ ││ │ │││ ││││││││││ │ │ 0000d638: 91044108 add x8, x8, #0x110
~ │ │ ││ │ │││ ││││││││││ │ │ 0000d63c: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │││ ││││││││││ │ │ __vgic_v3_perform_cpuif_access:1064.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_bpr0;
~ │ │ ││ │ │││ ││││││││││ │ ┌┼──0000d640: 14000005 b d654 <__vgic_v3_perform_cpuif_access+0x544>
│ │ ││ │ │││ ││││││││││ │ ││
│ │ ││ │ │││ ││││││││││ │ ││ __vgic_v3_perform_cpuif_access:1066.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_bpr0;
~ │ │ ││ │ │││ ││││││││││ │ │└─>0000d644: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d62c(b.cc)<__vgic_v3_perform_cpuif_access+0x534>
~ │ │ ││ │ │││ ││││││││││ │ │ 0000d648: 91065108 add x8, x8, #0x194
~ │ │ ││ │ │││ ││││││││││ │ │ 0000d64c: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ │││ ││││││││││ │ │ ┌─0000d650: 14000001 b d654 <__vgic_v3_perform_cpuif_access+0x544>
│ │ ││ │ │││ ││││││││││ │ │ │
│ │ ││ │ │││ ││││││││││ │ │ │ __vgic_v3_perform_cpuif_access:1067.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ │││ ││││││││││ │ ┌────────└>└>0000d654: 14000030 b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d640(b)<__vgic_v3_perform_cpuif_access+0x544>,0000d650(b)<__vgic_v3_perform_cpuif_access+0x544>
│ │ ││ │ │││ ││││││││││ │ │
│ │ ││ │ │││ ││││││││││ │ │ __vgic_v3_perform_cpuif_access:1069.7 (vgic-v3-sr.c) Sbepe if (║unlikely(is_read))
~ │ │ ││ │ │││ │││└┼┼┼┼┼┼──┼──┼───────────>0000d658: 394053e8 ldrb w8, [sp, #20] <- 0000d398(b.cc)<__vgic_v3_perform_cpuif_access+0x548>
│ │ ││ │ │││ │││ ││││││ │ │ __vgic_v3_perform_cpuif_access:1069.7 (vgic-v3-sr.c) sbepe if (║unlikely(is_read))
~ │ │ ││ │ │││ │││ ││││││ │ │ ┌──0000d65c: 360000a8 tbz w8, #0, d670 <__vgic_v3_perform_cpuif_access+0x560>
│ │ ││ │ │││ │││ ││││││ │ │ │
~ │ │ ││ │ │││ │││ ││││││ │ │ │┌─0000d660: 14000001 b d664 <__vgic_v3_perform_cpuif_access+0x554> <- 0000d65c(b.cc-succ)<fallthrough>
│ │ ││ │ │││ │││ ││││││ │ │ ││
~ │ │ ││ │ │││ │││ ││││││ │ │ │└>0000d664: 2a1f03e8 mov w8, wzr <- 0000d660(b)<__vgic_v3_perform_cpuif_access+0x554>
│ │ ││ │ │││ │││ ││││││ │ │ │ __vgic_v3_perform_cpuif_access:1070.4 (vgic-v3-sr.c) Sbepe ║return 0;
~ │ │ ││ │ │││ │││ ││││││ │ │ │ 0000d668: b9003fe8 str w8, [sp, #60]
~ │ │ ││ │ │││ │││ ││││││ ┌┼──┼─────────┼──0000d66c: 14000041 b d770 <__vgic_v3_perform_cpuif_access+0x660>
│ │ ││ │ │││ │││ ││││││ ││ │ │
│ │ ││ │ │││ │││ ││││││ ││ │ │ __vgic_v3_perform_cpuif_access:1071.6 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_dir;
~ │ │ ││ │ │││ │││ ││││││ ││ │ └─>0000d670: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d65c(b.cc)<__vgic_v3_perform_cpuif_access+0x560>
~ │ │ ││ │ │││ │││ ││││││ ││ │ 0000d674: 9109f108 add x8, x8, #0x27c
~ │ │ ││ │ │││ │││ ││││││ ││ │ 0000d678: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │││ │││ ││││││ ││ │ __vgic_v3_perform_cpuif_access:1072.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ │││ │││ ││││││ ││ │ ┌──────────0000d67c: 14000026 b d714 <__vgic_v3_perform_cpuif_access+0x604>
│ │ ││ │ │││ │││ ││││││ ││ │ │
│ │ ││ │ │││ │││ ││││││ ││ │ │ __vgic_v3_perform_cpuif_access:1074.7 (vgic-v3-sr.c) Sbepe if (║unlikely(!is_read))
~ │ │ ││ │ │││ │└┼─┼┼┼┼┼┼─┼┼──┼─┼─────────>0000d680: 394053e8 ldrb w8, [sp, #20] <- 0000d3b0(b.cc)<__vgic_v3_perform_cpuif_access+0x570>
│ │ ││ │ │││ │ │ ││││││ ││ │ │ __vgic_v3_perform_cpuif_access:1074.7 (vgic-v3-sr.c) sbepe if (║unlikely(!is_read))
~ │ │ ││ │ │││ │ │ ││││││ ││ │ │ ┌──0000d684: 370000a8 tbnz w8, #0, d698 <__vgic_v3_perform_cpuif_access+0x588>
│ │ ││ │ │││ │ │ ││││││ ││ │ │ │
~ │ │ ││ │ │││ │ │ ││││││ ││ │ │ │┌─0000d688: 14000001 b d68c <__vgic_v3_perform_cpuif_access+0x57c> <- 0000d684(b.cc-succ)<fallthrough>
│ │ ││ │ │││ │ │ ││││││ ││ │ │ ││
~ │ │ ││ │ │││ │ │ ││││││ ││ │ │ │└>0000d68c: 2a1f03e8 mov w8, wzr <- 0000d688(b)<__vgic_v3_perform_cpuif_access+0x57c>
│ │ ││ │ │││ │ │ ││││││ ││ │ │ │ __vgic_v3_perform_cpuif_access:1075.4 (vgic-v3-sr.c) Sbepe ║return 0;
~ │ │ ││ │ │││ │ │ ││││││ ││ │ │ │ 0000d690: b9003fe8 str w8, [sp, #60]
~ │ │ ││ │ │││ │ │ ││││││ ││ ┌┼─┼───────┼──0000d694: 14000037 b d770 <__vgic_v3_perform_cpuif_access+0x660>
│ │ ││ │ │││ │ │ ││││││ ││ ││ │ │
│ │ ││ │ │││ │ │ ││││││ ││ ││ │ │ __vgic_v3_perform_cpuif_access:1076.6 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_rpr;
~ │ │ ││ │ │││ │ │ ││││││ ││ ││ │ └─>0000d698: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d684(b.cc)<__vgic_v3_perform_cpuif_access+0x588>
~ │ │ ││ │ │││ │ │ ││││││ ││ ││ │ 0000d69c: 910d4108 add x8, x8, #0x350
~ │ │ ││ │ │││ │ │ ││││││ ││ ││ │ 0000d6a0: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │││ │ │ ││││││ ││ ││ │ __vgic_v3_perform_cpuif_access:1077.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ │││ │ │ ││││││ ││ ││ │ ┌────────0000d6a4: 1400001c b d714 <__vgic_v3_perform_cpuif_access+0x604>
│ │ ││ │ │││ │ │ ││││││ ││ ││ │ │
│ │ ││ │ │││ │ │ ││││││ ││ ││ │ │ __vgic_v3_perform_cpuif_access:1079.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ │││ │ │ ││││└┼─┼┼─┼┼─┼─┼───────>0000d6a8: 394053e8 ldrb w8, [sp, #20] <- 0000d428(b.cc)<__vgic_v3_perform_cpuif_access+0x598>
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ __vgic_v3_perform_cpuif_access:1079.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ ┌──0000d6ac: 360000c8 tbz w8, #0, d6c4 <__vgic_v3_perform_cpuif_access+0x5b4>
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │┌─0000d6b0: 14000001 b d6b4 <__vgic_v3_perform_cpuif_access+0x5a4> <- 0000d6ac(b.cc-succ)<fallthrough>
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ ││
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ ││ __vgic_v3_perform_cpuif_access:1080.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_ctlr;
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │└>0000d6b4: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d6b0(b)<__vgic_v3_perform_cpuif_access+0x5a4>
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │ 0000d6b8: 910f1108 add x8, x8, #0x3c4
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │ 0000d6bc: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │ __vgic_v3_perform_cpuif_access:1080.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_ctlr;
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ ┌┼──0000d6c0: 14000005 b d6d4 <__vgic_v3_perform_cpuif_access+0x5c4>
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ ││
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ ││ __vgic_v3_perform_cpuif_access:1082.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_ctlr;
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │└─>0000d6c4: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d6ac(b.cc)<__vgic_v3_perform_cpuif_access+0x5b4>
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │ 0000d6c8: 9112c108 add x8, x8, #0x4b0
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │ 0000d6cc: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │ ┌─0000d6d0: 14000001 b d6d4 <__vgic_v3_perform_cpuif_access+0x5c4>
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │ │
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │ │ __vgic_v3_perform_cpuif_access:1083.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ ┌──└>└>0000d6d4: 14000010 b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d6c0(b)<__vgic_v3_perform_cpuif_access+0x5c4>,0000d6d0(b)<__vgic_v3_perform_cpuif_access+0x5c4>
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │
│ │ ││ │ │││ │ │ ││││ │ ││ ││ │ │ │ __vgic_v3_perform_cpuif_access:1085.7 (vgic-v3-sr.c) Sbepe if (║is_read)
~ │ │ ││ │ │└┼─┼─┼─┼┼┼┼─┼─┼┼─┼┼─┼─┼─┼─────>0000d6d8: 394053e8 ldrb w8, [sp, #20] <- 0000d260(b.cc)<__vgic_v3_perform_cpuif_access+0x5c8>
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ __vgic_v3_perform_cpuif_access:1085.7 (vgic-v3-sr.c) sbepe if (║is_read)
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ ┌──0000d6dc: 360000c8 tbz w8, #0, d6f4 <__vgic_v3_perform_cpuif_access+0x5e4>
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ │
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ │┌─0000d6e0: 14000001 b d6e4 <__vgic_v3_perform_cpuif_access+0x5d4> <- 0000d6dc(b.cc-succ)<fallthrough>
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ ││
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ ││ __vgic_v3_perform_cpuif_access:1086.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_read_pmr;
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ │└>0000d6e4: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d6e0(b)<__vgic_v3_perform_cpuif_access+0x5d4>
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ │ 0000d6e8: 91163108 add x8, x8, #0x58c
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ │ 0000d6ec: f9000fe8 str x8, [sp, #24]
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ │ __vgic_v3_perform_cpuif_access:1086.4 (vgic-v3-sr.c) sbepe ║fn = __vgic_v3_read_pmr;
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │┌──┼──0000d6f0: 14000005 b d704 <__vgic_v3_perform_cpuif_access+0x5f4>
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ ││ │
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ ││ │ __vgic_v3_perform_cpuif_access:1088.7 (vgic-v3-sr.c) Sbepe fn ║= __vgic_v3_write_pmr;
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ ││ └─>0000d6f4: b0000008 adrp x8, e000 <__vgic_v3_read_hppir+0xd0> <- 0000d6dc(b.cc)<__vgic_v3_perform_cpuif_access+0x5e4>
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ ││ 0000d6f8: 91181108 add x8, x8, #0x604
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ ││ 0000d6fc: f9000fe8 str x8, [sp, #24]
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ ││ ┌─0000d700: 14000001 b d704 <__vgic_v3_perform_cpuif_access+0x5f4>
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ ││ │
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ ││ │ __vgic_v3_perform_cpuif_access:1089.3 (vgic-v3-sr.c) Sbepe ║break;
~ │ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │└>┌─└>0000d704: 14000004 b d714 <__vgic_v3_perform_cpuif_access+0x604> <- 0000d6f0(b)<__vgic_v3_perform_cpuif_access+0x5f4>,0000d700(b)<__vgic_v3_perform_cpuif_access+0x5f4>
│ │ ││ │ │ │ │ │ ││││ │ ││ ││ │ │ │ │
~ │ │ ││ │ │ │ │ │ ││└┼─┼─┼┼─┼┼─┼─┼─┼──┼──>0000d708: 2a1f03e8 mov w8, wzr <- 0000d45c(b)<__vgic_v3_perform_cpuif_access+0x5f8>
│ │ ││ │ │ │ │ │ ││ │ │ ││ ││ │ │ │ │ __vgic_v3_perform_cpuif_access:1091.3 (vgic-v3-sr.c) Sbepe ║return 0;
~ │ │ ││ │ │ │ │ │ ││ │ │ ││ ││ │ │ │ │ 0000d70c: b9003fe8 str w8, [sp, #60]
~ │ │ ││ │ │ │ │ │ ││ │ │ ││ ││ │ │ │┌─┼───0000d710: 14000018 b d770 <__vgic_v3_perform_cpuif_access+0x660>
│ │ ││ │ │ │ │ │ ││ │ │ ││ ││ │ │ ││ │
│ │ ││ │ │ │ │ │ ││ │ │ ││ ││ │ │ ││ │ __vgic_v3_perform_cpuif_access:1094.9 (vgic-v3-sr.c) Sbepe vmcr = ║__vgic_v3_read_vmcr();
~ │ │ │└>└>└>└>└>└>│└>└>└>│└>│└>└>└>└┼>└──>0000d714: 97fffe6c bl d0c4 <__vgic_v3_read_vmcr> <- 0000d484(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d4ac(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d4dc(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d50c(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d53c(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d56c(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d59c(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d5cc(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d5f4(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d624(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d654(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d67c(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d6a4(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d6d4(b)<__vgic_v3_perform_cpuif_access+0x604>,0000d704(b)<__vgic_v3_perform_cpuif_access+0x604>
│ │ │ │ │ │ │
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1094.7 (vgic-v3-sr.c) sbepe vmcr ║= __vgic_v3_read_vmcr();
~ │ │ │ │ │ │ │ 0000d718: b90027e0 str w0, [sp, #36] <- 0000d714(bl-succ)<return>
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1095.27 (vgic-v3-sr.c) Sbepe rt = kvm_vcpu_sys_get_rt(║vcpu);
~ │ │ │ │ │ │ │ 0000d71c: f9401be8 ldr x8, [sp, #48]
~ │ │ │ │ │ │ │ 0000d720: f81f03a8 stur x8, [x29, #-16]
l: 0xd724 0xd744 kvm_vcpu_sys_get_rt inlined from __vgic_v3_perform_cpuif_access:1095 (vgic-v3-sr.c) <a86a9>:
l │ │ │ │ │ │ │ kvm_vcpu_sys_get_rt:360.29 (kvm_emulate.h) Sbepe u32 esr = kvm_vcpu_get_esr(║vcpu);
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd724 0xd744 (DW_OP_fbreg -0x10) kvm_vcpu_sys_get_rt(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+esr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd724 0xd744 (DW_OP_fbreg -0x14) kvm_vcpu_sys_get_rt(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~l │ │ │ │ │ │ │ 0000d724: f85f03a8 ldur x8, [x29, #-16]
~l │ │ │ │ │ │ │ 0000d728: f81f83a8 stur x8, [x29, #-8]
m: 0xd72c 0xd734 kvm_vcpu_get_esr inlined from kvm_vcpu_sys_get_rt:360 (kvm_emulate.h) <a86ce>:<a86a9>:
lm │ │ │ │ │ │ │ kvm_vcpu_get_esr:224.9 (kvm_emulate.h) Sbepe return ║vcpu->arch.fault.esr_el2;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd72c 0xd734 (DW_OP_fbreg -0x8) kvm_vcpu_get_esr(inlined):kvm_vcpu_sys_get_rt(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~lm │ │ │ │ │ │ │ 0000d72c: f85f83a8 ldur x8, [x29, #-8]
lm │ │ │ │ │ │ │ kvm_vcpu_get_esr:224.26 (kvm_emulate.h) sbepe return vcpu->arch.fault.║esr_el2;
~lm │ │ │ │ │ │ │ 0000d730: b9488909 ldr w9, [x8, #2184]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd72c 0xd734 (DW_OP_fbreg -0x8) kvm_vcpu_get_esr(inlined):kvm_vcpu_sys_get_rt(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
l │ │ │ │ │ │ │ kvm_vcpu_sys_get_rt:360.6 (kvm_emulate.h) Sbepe u32 ║esr = kvm_vcpu_get_esr(vcpu);
~l │ │ │ │ │ │ │ 0000d734: b81ec3a9 stur w9, [x29, #-20]
l │ │ │ │ │ │ │ kvm_vcpu_sys_get_rt:361.9 (kvm_emulate.h) Sbepe return ║ESR_ELx_SYS64_ISS_RT(esr);
~l │ │ │ │ │ │ │ 0000d738: b85ec3a9 ldur w9, [x29, #-20]
~l │ │ │ │ │ │ │ 0000d73c: 2a0903e8 mov w8, w9
~l │ │ │ │ │ │ │ 0000d740: d3452508 ubfx x8, x8, #5, #5
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd724 0xd744 (DW_OP_fbreg -0x10) kvm_vcpu_sys_get_rt(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-esr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd724 0xd744 (DW_OP_fbreg -0x14) kvm_vcpu_sys_get_rt(inlined):__vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1095.5 (vgic-v3-sr.c) Sbepe rt ║= kvm_vcpu_sys_get_rt(vcpu);
~ │ │ │ │ │ │ │ 0000d744: b9002fe8 str w8, [sp, #44]
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1096.2 (vgic-v3-sr.c) Sbepe ║fn(vcpu, vmcr, rt);
~ │ │ │ │ │ │ │ 0000d748: f9400fea ldr x10, [sp, #24]
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1096.5 (vgic-v3-sr.c) sbepe fn(║vcpu, vmcr, rt);
~ │ │ │ │ │ │ │ 0000d74c: f9401be0 ldr x0, [sp, #48]
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1096.11 (vgic-v3-sr.c) sbepe fn(vcpu, ║vmcr, rt);
~ │ │ │ │ │ │ │ 0000d750: b94027e1 ldr w1, [sp, #36]
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1096.17 (vgic-v3-sr.c) sbepe fn(vcpu, vmcr, ║rt);
~ │ │ │ │ │ │ │ 0000d754: b9402fe2 ldr w2, [sp, #44]
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1096.2 (vgic-v3-sr.c) sbepe ║fn(vcpu, vmcr, rt);
~ │ │ │ │ │ │ │ 0000d758: d63f0140 blr x10
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1098.19 (vgic-v3-sr.c) Sbepe __kvm_skip_instr(║vcpu);
~ │ │ │ │ │ │ │ 0000d75c: f9401be0 ldr x0, [sp, #48]
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1098.2 (vgic-v3-sr.c) sbepe ║__kvm_skip_instr(vcpu);
~ │ │ │ │ │ │ │ 0000d760: 94000008 bl d780 <__kvm_skip_instr>
│ │ │ │ │ │ │
~ │ │ │ │ │ │ │ 0000d764: 52800028 mov w8, #0x1 // #1 <- 0000d760(bl-succ)<return>
│ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1100.2 (vgic-v3-sr.c) Sbepe ║return 1;
~ │ │ │ │ │ │ │ 0000d768: b9003fe8 str w8, [sp, #60]
~ │ │ │ │ │ │ │ ┌─0000d76c: 14000001 b d770 <__vgic_v3_perform_cpuif_access+0x660>
│ │ │ │ │ │ │ │
│ │ │ │ │ │ │ │ __vgic_v3_perform_cpuif_access:1101.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>└───────────>└─────>└─>└──────>└──>└>0000d770: b9403fe0 ldr w0, [sp, #60] <- 0000d1b8(b)<__vgic_v3_perform_cpuif_access+0x660>,0000d474(b)<__vgic_v3_perform_cpuif_access+0x660>,0000d49c(b)<__vgic_v3_perform_cpuif_access+0x660>,0000d5e4(b)<__vgic_v3_perform_cpuif_access+0x660>,0000d66c(b)<__vgic_v3_perform_cpuif_access+0x660>,0000d694(b)<__vgic_v3_perform_cpuif_access+0x660>,0000d710(b)<__vgic_v3_perform_cpuif_access+0x660>,0000d76c(b)<__vgic_v3_perform_cpuif_access+0x660>
~ 0000d774: a9497bfd ldp x29, x30, [sp, #144]
~ 0000d778: 910283ff add sp, sp, #0xa0
0000d11c CFA:r29+16 r29:c-16 r30:c-8
~ 0000d77c: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd110 0xd780 (DW_OP_breg31 0x30) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:974
-rt var int (base type, DW_ATE_signed size:4) 0xd110 0xd780 (DW_OP_breg31 0x2c) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:976
-esr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd110 0xd780 (DW_OP_breg31 0x28) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:977
-vmcr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd110 0xd780 (DW_OP_breg31 0x24) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:978
-fn var pointer(subroutine(prototyped no type(pointer(struct kvm_vcpu<99433>/<9a302>),typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))),int (base type, DW_ATE_signed size:4))) 0xd110 0xd780 (DW_OP_breg31 0x18) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:979
-is_read var typedef(bool=_Bool (base type, DW_ATE_boolean size:1)) 0xd110 0xd780 (DW_OP_breg31 0x14) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:980
-sysreg var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd110 0xd780 (DW_OP_breg31 0x10) __vgic_v3_perform_cpuif_access:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:981
**0000d780 <__kvm_skip_instr>:
+ __kvm_skip_instr params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd780 0xd824 (DW_OP_fbreg -0x18)
__kvm_skip_instr:36.0 (adjust_pc.h) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd780 0xd824 (DW_OP_fbreg -0x18) __kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:35
~ 0000d780: d10183ff sub sp, sp, #0x60 <- 0000d1ac(bl)<__kvm_skip_instr>,0000d760(bl)<__kvm_skip_instr>
~ 0000d784: a9057bfd stp x29, x30, [sp, #80]
0000d780 CFA:r31 r29:u r30:u
~ 0000d788: 910143fd add x29, sp, #0x50
~ 0000d78c: f81e83a0 stur x0, [x29, #-24]
+reg var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd790 0xd7a4 (DW_OP_fbreg -0x20) lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:37
~ 0000d790: d53c4028 mrs x8, elr_el2
__kvm_skip_instr:37.19 (adjust_pc.h) SbePe *vcpu_pc(vcpu) = ║read_sysreg_el2(SYS_ELR);
~ 0000d794: f81e03a8 stur x8, [x29, #-32]
~ 0000d798: f85e03a8 ldur x8, [x29, #-32]
~ 0000d79c: f90017e8 str x8, [sp, #40]
~ 0000d7a0: f94017e8 ldr x8, [sp, #40]
-reg var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd790 0xd7a4 (DW_OP_fbreg -0x20) lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:37
__kvm_skip_instr:37.11 (adjust_pc.h) sbepe *vcpu_pc(║vcpu) = read_sysreg_el2(SYS_ELR);
~ 0000d7a4: f85e83a9 ldur x9, [x29, #-24]
~ 0000d7a8: f81f03a9 stur x9, [x29, #-16]
n: 0xd7ac 0xd7b0 vcpu_pc inlined from __kvm_skip_instr:37 (adjust_pc.h) <a8745>:
n vcpu_pc:132.27 (kvm_emulate.h) Sbepe return (unsigned long *)&║vcpu_gp_regs(vcpu)->pc;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd7ac 0xd7b0 (DW_OP_fbreg -0x10) vcpu_pc(inlined):__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~n 0000d7ac: f85f03a9 ldur x9, [x29, #-16]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd7ac 0xd7b0 (DW_OP_fbreg -0x10) vcpu_pc(inlined):__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
__kvm_skip_instr:37.17 (adjust_pc.h) Sbepe *vcpu_pc(vcpu) ║= read_sysreg_el2(SYS_ELR);
~ 0000d7b0: f9013128 str x8, [x9, #608]
+reg var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd7b4 0xd7c8 (DW_OP_breg31 0x20) lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:38
~ 0000d7b4: d53c4008 mrs x8, spsr_el2
__kvm_skip_instr:38.31 (adjust_pc.h) Sbepe vcpu_gp_regs(vcpu)->pstate = ║read_sysreg_el2(SYS_SPSR);
~ 0000d7b8: f90013e8 str x8, [sp, #32]
~ 0000d7bc: f94013e8 ldr x8, [sp, #32]
~ 0000d7c0: f9000fe8 str x8, [sp, #24]
~ 0000d7c4: f9400fe8 ldr x8, [sp, #24]
-reg var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd7b4 0xd7c8 (DW_OP_breg31 0x20) lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:38
__kvm_skip_instr:38.2 (adjust_pc.h) sbepe ║vcpu_gp_regs(vcpu)->pstate = read_sysreg_el2(SYS_SPSR);
~ 0000d7c8: f85e83a9 ldur x9, [x29, #-24]
__kvm_skip_instr:38.29 (adjust_pc.h) sbepe vcpu_gp_regs(vcpu)->pstate ║= read_sysreg_el2(SYS_SPSR);
~ 0000d7cc: f9013528 str x8, [x9, #616]
__kvm_skip_instr:40.17 (adjust_pc.h) Sbepe kvm_skip_instr(║vcpu);
~ 0000d7d0: f85e83a0 ldur x0, [x29, #-24]
__kvm_skip_instr:40.2 (adjust_pc.h) sbepe ║kvm_skip_instr(vcpu);
~ 0000d7d4: 940003bc bl e6c4 <kvm_skip_instr>
__kvm_skip_instr:42.2 (adjust_pc.h) Sbepe ║write_sysreg_el2(vcpu_gp_regs(vcpu)->pstate, SYS_SPSR);
~ ┌─0000d7d8: 14000001 b d7dc <__kvm_skip_instr+0x5c> <- 0000d7d4(bl-succ)<return>
│
│ __kvm_skip_instr:42.2 (adjust_pc.h) sbepe ║write_sysreg_el2(vcpu_gp_regs(vcpu)->pstate, SYS_SPSR);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd7dc 0xd7f4 (DW_OP_breg31 0x10) lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:42
~ └>0000d7dc: f85e83a8 ldur x8, [x29, #-24] <- 0000d7d8(b)<__kvm_skip_instr+0x5c>
~ 0000d7e0: f9413508 ldr x8, [x8, #616]
~ 0000d7e4: f9000be8 str x8, [sp, #16]
~ 0000d7e8: f9400be8 ldr x8, [sp, #16]
~ 0000d7ec: d51c4008 msr spsr_el2, x8
~ ┌─0000d7f0: 14000001 b d7f4 <__kvm_skip_instr+0x74>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd7dc 0xd7f4 (DW_OP_breg31 0x10) lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:42
│
│ __kvm_skip_instr:43.2 (adjust_pc.h) Sbepe ║write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
~ ┌─└>0000d7f4: 14000001 b d7f8 <__kvm_skip_instr+0x78> <- 0000d7f0(b)<__kvm_skip_instr+0x74>
│
│ __kvm_skip_instr:43.2 (adjust_pc.h) sbepe ║write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd7f8 0xd818 (DW_OP_breg31 0x8) lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:43
~ └──>0000d7f8: f85e83a8 ldur x8, [x29, #-24] <- 0000d7f4(b)<__kvm_skip_instr+0x78>
~ 0000d7fc: f81f83a8 stur x8, [x29, #-8]
o: 0xd800 0xd804 vcpu_pc inlined from __kvm_skip_instr:43 (adjust_pc.h) <a87b5>:<lexical_block>:
o vcpu_pc:132.27 (kvm_emulate.h) Sbepe return (unsigned long *)&║vcpu_gp_regs(vcpu)->pc;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd800 0xd804 (DW_OP_fbreg -0x8) vcpu_pc(inlined):lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~o 0000d800: f85f83a8 ldur x8, [x29, #-8]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xd800 0xd804 (DW_OP_fbreg -0x8) vcpu_pc(inlined):lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
__kvm_skip_instr:43.2 (adjust_pc.h) Sbepe ║write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
~ 0000d804: f9413108 ldr x8, [x8, #608]
~ 0000d808: f90007e8 str x8, [sp, #8]
~ 0000d80c: f94007e8 ldr x8, [sp, #8]
~ 0000d810: d51c4028 msr elr_el2, x8
~ ┌─0000d814: 14000001 b d818 <__kvm_skip_instr+0x98>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd7f8 0xd818 (DW_OP_breg31 0x8) lexblock:__kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:43
│
│ __kvm_skip_instr:44.1 (adjust_pc.h) Sbepe ║}
~ └>0000d818: a9457bfd ldp x29, x30, [sp, #80] <- 0000d814(b)<__kvm_skip_instr+0x98>
~ 0000d81c: 910183ff add sp, sp, #0x60
0000d78c CFA:r29+16 r29:c-16 r30:c-8
~ 0000d820: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd780 0xd824 (DW_OP_fbreg -0x18) __kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:35
**0000d824 <__vgic_v3_read_iar>:
+ __vgic_v3_read_iar params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd824 0xd9d8 (DW_OP_breg31 0x28)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd824 0xd9d8 (DW_OP_breg31 0x24)
+rt param int (base type, DW_ATE_signed size:4) 0xd824 0xd9d8 (DW_OP_breg31 0x20)
__vgic_v3_read_iar:630.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd824 0xd9d8 (DW_OP_breg31 0x28) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:629
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd824 0xd9d8 (DW_OP_breg31 0x24) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:629
+rt param int (base type, DW_ATE_signed size:4) 0xd824 0xd9d8 (DW_OP_breg31 0x20) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:629
+lr_val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd824 0xd9d8 (DW_OP_breg31 0x18) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:631
+lr_prio var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd824 0xd9d8 (DW_OP_breg31 0x14) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:632
+pmr var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd824 0xd9d8 (DW_OP_breg31 0x10) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:632
+lr var int (base type, DW_ATE_signed size:4) 0xd824 0xd9d8 (DW_OP_breg31 0xc) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:633
+grp var int (base type, DW_ATE_signed size:4) 0xd824 0xd9d8 (DW_OP_breg31 0x8) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:633
~ 0000d824: d101c3ff sub sp, sp, #0x70
~ 0000d828: a9067bfd stp x29, x30, [sp, #96]
0000d824 CFA:r31 r29:u r30:u
~ 0000d82c: 910183fd add x29, sp, #0x60
~ 0000d830: f90017e0 str x0, [sp, #40]
~ 0000d834: b90027e1 str w1, [sp, #36]
~ 0000d838: b90023e2 str w2, [sp, #32]
__vgic_v3_read_iar:635.28 (vgic-v3-sr.c) SbePe grp = __vgic_v3_get_group(║vcpu);
~ 0000d83c: f94017e0 ldr x0, [sp, #40]
__vgic_v3_read_iar:635.8 (vgic-v3-sr.c) sbepe grp = ║__vgic_v3_get_group(vcpu);
~ 0000d840: 940003c6 bl e758 <__vgic_v3_get_group>
__vgic_v3_read_iar:635.6 (vgic-v3-sr.c) sbepe grp ║= __vgic_v3_get_group(vcpu);
~ 0000d844: b9000be0 str w0, [sp, #8] <- 0000d840(bl-succ)<return>
__vgic_v3_read_iar:637.37 (vgic-v3-sr.c) Sbepe lr = __vgic_v3_highest_priority_lr(║vcpu, vmcr, &lr_val);
~ 0000d848: f94017e0 ldr x0, [sp, #40]
__vgic_v3_read_iar:637.43 (vgic-v3-sr.c) sbepe lr = __vgic_v3_highest_priority_lr(vcpu, ║vmcr, &lr_val);
~ 0000d84c: b94027e1 ldr w1, [sp, #36]
~ 0000d850: 910063e2 add x2, sp, #0x18
__vgic_v3_read_iar:637.7 (vgic-v3-sr.c) sbepe lr = ║__vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
~ 0000d854: 940003d1 bl e798 <__vgic_v3_highest_priority_lr>
__vgic_v3_read_iar:637.5 (vgic-v3-sr.c) sbepe lr ║= __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
~ 0000d858: b9000fe0 str w0, [sp, #12] <- 0000d854(bl-succ)<return>
__vgic_v3_read_iar:638.6 (vgic-v3-sr.c) Sbepe if (║lr < 0)
~ 0000d85c: b9400fe8 ldr w8, [sp, #12]
__vgic_v3_read_iar:638.6 (vgic-v3-sr.c) sbepe if (║lr < 0)
~ ┌──0000d860: 36f80068 tbz w8, #31, d86c <__vgic_v3_read_iar+0x48>
│
~ │┌─0000d864: 14000001 b d868 <__vgic_v3_read_iar+0x44> <- 0000d860(b.cc-succ)<fallthrough>
││
││ __vgic_v3_read_iar:639.3 (vgic-v3-sr.c) Sbepe ║goto spurious;
~ ┌────────┼└>0000d868: 14000046 b d980 <__vgic_v3_read_iar+0x15c> <- 0000d864(b)<__vgic_v3_read_iar+0x44>
│ │
│ │ __vgic_v3_read_iar:641.6 (vgic-v3-sr.c) Sbepe if (║grp != !!(lr_val & ICH_LR_GROUP))
~ │ └─>0000d86c: b9400be8 ldr w8, [sp, #8] <- 0000d860(b.cc)<__vgic_v3_read_iar+0x48>
│ __vgic_v3_read_iar:641.14 (vgic-v3-sr.c) sbepe if (grp != !║!(lr_val & ICH_LR_GROUP))
~ │ 0000d870: 39407fe9 ldrb w9, [sp, #31]
~ │ 0000d874: 121c0129 and w9, w9, #0x10
│ __vgic_v3_read_iar:641.6 (vgic-v3-sr.c) sbepe if (║grp != !!(lr_val & ICH_LR_GROUP))
~ │ 0000d878: 6b491108 subs w8, w8, w9, lsr #4
~ │ ┌──0000d87c: 54000060 b.eq d888 <__vgic_v3_read_iar+0x64> // b.none
│ │
~ │ │┌─0000d880: 14000001 b d884 <__vgic_v3_read_iar+0x60> <- 0000d87c(b.cc-succ)<fallthrough>
│ ││
│ ││ __vgic_v3_read_iar:642.3 (vgic-v3-sr.c) Sbepe ║goto spurious;
~ │ ┌──────┼└>0000d884: 1400003f b d980 <__vgic_v3_read_iar+0x15c> <- 0000d880(b)<__vgic_v3_read_iar+0x60>
│ │ │
│ │ │ __vgic_v3_read_iar:644.9 (vgic-v3-sr.c) Sbepe pmr = (║vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
~ │ │ └─>0000d888: 39409fe8 ldrb w8, [sp, #39] <- 0000d87c(b.cc)<__vgic_v3_read_iar+0x64>
~ │ │ 0000d88c: 2a0803e0 mov w0, w8
│ │ __vgic_v3_read_iar:644.6 (vgic-v3-sr.c) sbepe pmr ║= (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
~ │ │ 0000d890: 390043e0 strb w0, [sp, #16]
│ │ __vgic_v3_read_iar:645.13 (vgic-v3-sr.c) Sbepe lr_prio = (║lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
~ │ │ 0000d894: 79403fe8 ldrh w8, [sp, #30]
~ │ │ 0000d898: 2a0803e1 mov w1, w8
│ │ __vgic_v3_read_iar:645.10 (vgic-v3-sr.c) sbepe lr_prio ║= (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
~ │ │ 0000d89c: 390053e1 strb w1, [sp, #20]
│ │ __vgic_v3_read_iar:646.6 (vgic-v3-sr.c) Sbepe if (║pmr <= lr_prio)
~ │ │ 0000d8a0: 394043e8 ldrb w8, [sp, #16]
│ │ __vgic_v3_read_iar:646.13 (vgic-v3-sr.c) sbepe if (pmr <= ║lr_prio)
~ │ │ 0000d8a4: 394053e9 ldrb w9, [sp, #20]
│ │ __vgic_v3_read_iar:646.6 (vgic-v3-sr.c) sbepe if (║pmr <= lr_prio)
~ │ │ 0000d8a8: 6b090108 subs w8, w8, w9
~ │ │ ┌──0000d8ac: 5400006c b.gt d8b8 <__vgic_v3_read_iar+0x94>
│ │ │
~ │ │ │┌─0000d8b0: 14000001 b d8b4 <__vgic_v3_read_iar+0x90> <- 0000d8ac(b.cc-succ)<fallthrough>
│ │ ││
│ │ ││ __vgic_v3_read_iar:647.3 (vgic-v3-sr.c) Sbepe ║goto spurious;
~ │ │ ┌────┼└>0000d8b4: 14000033 b d980 <__vgic_v3_read_iar+0x15c> <- 0000d8b0(b)<__vgic_v3_read_iar+0x90>
│ │ │ │
│ │ │ │ __vgic_v3_read_iar:649.6 (vgic-v3-sr.c) Sbepe if (║__vgic_v3_get_highest_active_priority() <= __vgic_v3_pri_to_pre(lr_prio, vmcr, grp))
~ │ │ │ └─>0000d8b8: 94000406 bl e8d0 <__vgic_v3_get_highest_active_priority> <- 0000d8ac(b.cc)<__vgic_v3_read_iar+0x94>
│ │ │
│ │ │ __vgic_v3_read_iar:649.79 (vgic-v3-sr.c) sbepe if (__vgic_v3_get_highest_active_priority() <= __vgic_v3_pri_to_pre(lr_prio, ║vmcr, grp))
~ │ │ │ 0000d8bc: b94027e1 ldr w1, [sp, #36] <- 0000d8b8(bl-succ)<return>
│ │ │ __vgic_v3_read_iar:649.85 (vgic-v3-sr.c) sbepe if (__vgic_v3_get_highest_active_priority() <= __vgic_v3_pri_to_pre(lr_prio, vmcr, ║grp))
~ │ │ │ 0000d8c0: b9400be2 ldr w2, [sp, #8]
│ │ │ __vgic_v3_read_iar:649.49 (vgic-v3-sr.c) sbepe if (__vgic_v3_get_highest_active_priority() <= ║__vgic_v3_pri_to_pre(lr_prio, vmcr, grp))
~ │ │ │ 0000d8c4: 394053e8 ldrb w8, [sp, #20]
~ │ │ │ 0000d8c8: b90007e0 str w0, [sp, #4]
~ │ │ │ 0000d8cc: 2a0803e0 mov w0, w8
~ │ │ │ 0000d8d0: 94000440 bl e9d0 <__vgic_v3_pri_to_pre>
│ │ │
~ │ │ │ 0000d8d4: b94007e8 ldr w8, [sp, #4] <- 0000d8d0(bl-succ)<return>
│ │ │ __vgic_v3_read_iar:649.6 (vgic-v3-sr.c) sbepe if (║__vgic_v3_get_highest_active_priority() <= __vgic_v3_pri_to_pre(lr_prio, vmcr, grp))
~ │ │ │ 0000d8d8: 6b200109 subs w9, w8, w0, uxtb
~ │ │ │ ┌──0000d8dc: 5400006c b.gt d8e8 <__vgic_v3_read_iar+0xc4>
│ │ │ │
~ │ │ │ │┌─0000d8e0: 14000001 b d8e4 <__vgic_v3_read_iar+0xc0> <- 0000d8dc(b.cc-succ)<fallthrough>
│ │ │ ││
│ │ │ ││ __vgic_v3_read_iar:650.3 (vgic-v3-sr.c) Sbepe ║goto spurious;
~ │ │ │ ┌─┼└>0000d8e4: 14000027 b d980 <__vgic_v3_read_iar+0x15c> <- 0000d8e0(b)<__vgic_v3_read_iar+0xc0>
│ │ │ │ │
│ │ │ │ │ __vgic_v3_read_iar:652.9 (vgic-v3-sr.c) Sbepe lr_val ║&= ~ICH_LR_STATE;
~ │ │ │ │ └─>0000d8e8: f9400fe8 ldr x8, [sp, #24] <- 0000d8dc(b.cc)<__vgic_v3_read_iar+0xc4>
~ │ │ │ │ 0000d8ec: 9240f508 and x8, x8, #0x3fffffffffffffff
~ │ │ │ │ 0000d8f0: f9000fe8 str x8, [sp, #24]
│ │ │ │ __vgic_v3_read_iar:654.7 (vgic-v3-sr.c) Sbepe if ((║lr_val & ICH_LR_VIRTUAL_ID_MASK) <= VGIC_MAX_SPI)
~ │ │ │ │ 0000d8f4: b9401be9 ldr w9, [sp, #24]
~ │ │ │ │ 0000d8f8: 2a0903e8 mov w8, w9
│ │ │ │ __vgic_v3_read_iar:654.6 (vgic-v3-sr.c) sbepe if (║(lr_val & ICH_LR_VIRTUAL_ID_MASK) <= VGIC_MAX_SPI)
~ │ │ │ │ 0000d8fc: f10fed08 subs x8, x8, #0x3fb
~ │ │ │ │┌───0000d900: 540000c8 b.hi d918 <__vgic_v3_read_iar+0xf4> // b.pmore
│ │ │ ││
~ │ │ │ ││ ┌─0000d904: 14000001 b d908 <__vgic_v3_read_iar+0xe4> <- 0000d900(b.cc-succ)<fallthrough>
│ │ │ ││ │
│ │ │ ││ │ __vgic_v3_read_iar:655.10 (vgic-v3-sr.c) Sbepe lr_val ║|= ICH_LR_ACTIVE_BIT;
~ │ │ │ ││ └>0000d908: f9400fe8 ldr x8, [sp, #24] <- 0000d904(b)<__vgic_v3_read_iar+0xe4>
~ │ │ │ ││ 0000d90c: b2410108 orr x8, x8, #0x8000000000000000
~ │ │ │ ││ 0000d910: f9000fe8 str x8, [sp, #24]
│ │ │ ││ __vgic_v3_read_iar:655.3 (vgic-v3-sr.c) sbepe ║lr_val |= ICH_LR_ACTIVE_BIT;
~ │ │ │ ││ ┌─0000d914: 14000001 b d918 <__vgic_v3_read_iar+0xf4>
│ │ │ ││ │
│ │ │ ││ │ __vgic_v3_read_iar:656.18 (vgic-v3-sr.c) Sbepe __gic_v3_set_lr(║lr_val, lr);
~ │ │ │ │└>└>0000d918: f9400fe0 ldr x0, [sp, #24] <- 0000d900(b.cc)<__vgic_v3_read_iar+0xf4>,0000d914(b)<__vgic_v3_read_iar+0xf4>
│ │ │ │ __vgic_v3_read_iar:656.26 (vgic-v3-sr.c) sbepe __gic_v3_set_lr(lr_val, ║lr);
~ │ │ │ │ 0000d91c: b9400fe1 ldr w1, [sp, #12]
│ │ │ │ __vgic_v3_read_iar:656.2 (vgic-v3-sr.c) sbepe ║__gic_v3_set_lr(lr_val, lr);
~ │ │ │ │ 0000d920: 97fffb29 bl c5c4 <__gic_v3_set_lr>
│ │ │ │
│ │ │ │ __vgic_v3_read_iar:657.41 (vgic-v3-sr.c) Sbepe __vgic_v3_set_active_priority(lr_prio, ║vmcr, grp);
~ │ │ │ │ 0000d924: b94027e1 ldr w1, [sp, #36] <- 0000d920(bl-succ)<return>
│ │ │ │ __vgic_v3_read_iar:657.47 (vgic-v3-sr.c) sbepe __vgic_v3_set_active_priority(lr_prio, vmcr, ║grp);
~ │ │ │ │ 0000d928: b9400be2 ldr w2, [sp, #8]
│ │ │ │ __vgic_v3_read_iar:657.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_set_active_priority(lr_prio, vmcr, grp);
~ │ │ │ │ 0000d92c: 394053e0 ldrb w0, [sp, #20]
~ │ │ │ │ 0000d930: 94000444 bl ea40 <__vgic_v3_set_active_priority>
│ │ │ │
│ │ │ │ __vgic_v3_read_iar:658.15 (vgic-v3-sr.c) Sbepe vcpu_set_reg(║vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
~ │ │ │ │ 0000d934: f94017e8 ldr x8, [sp, #40] <- 0000d930(bl-succ)<return>
│ │ │ │ __vgic_v3_read_iar:658.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
~ │ │ │ │ 0000d938: b94023e9 ldr w9, [sp, #32]
│ │ │ │ __vgic_v3_read_iar:658.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║lr_val & ICH_LR_VIRTUAL_ID_MASK);
~ │ │ │ │ 0000d93c: b9401bea ldr w10, [sp, #24]
~ │ │ │ │ 0000d940: 2a0a03eb mov w11, w10
~ │ │ │ │ 0000d944: f81e03a8 stur x8, [x29, #-32]
~ │ │ │ │ 0000d948: 381dc3a9 sturb w9, [x29, #-36]
~ │ │ │ │ 0000d94c: f9001beb str x11, [sp, #48]
p: 0xd950 0xd97c vcpu_set_reg inlined from __vgic_v3_read_iar:658 (vgic-v3-sr.c) <a889c>:
p │ │ │ │ vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd950 0xd97c (DW_OP_fbreg -0x20) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd950 0xd97c (DW_OP_fbreg -0x24) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xd950 0xd97c (DW_OP_breg31 0x30) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~p │ │ │ │ 0000d950: 385dc3a9 ldurb w9, [x29, #-36]
p │ │ │ │ vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~p │ │ │ │ 0000d954: 71007d29 subs w9, w9, #0x1f
~p │ │ │ │┌───0000d958: 54000120 b.eq d97c <__vgic_v3_read_iar+0x158> // b.none
│ │ │ ││
~p │ │ │ ││ ┌─0000d95c: 14000001 b d960 <__vgic_v3_read_iar+0x13c> <- 0000d958(b.cc-succ)<fallthrough>
│ │ │ ││ │
p │ │ │ ││ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~p │ │ │ ││ └>0000d960: f9401be8 ldr x8, [sp, #48] <- 0000d95c(b)<__vgic_v3_read_iar+0x13c>
p │ │ │ ││ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~p │ │ │ ││ 0000d964: f85e03a9 ldur x9, [x29, #-32]
p │ │ │ ││ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~p │ │ │ ││ 0000d968: 385dc3aa ldurb w10, [x29, #-36]
~p │ │ │ ││ 0000d96c: 2a0a03eb mov w11, w10
p │ │ │ ││ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~p │ │ │ ││ 0000d970: 8b0b0d29 add x9, x9, x11, lsl #3
p │ │ │ ││ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~p │ │ │ ││ 0000d974: f900b128 str x8, [x9, #352]
p │ │ │ ││ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~p │ │ │ ││ ┌─0000d978: 14000001 b d97c <__vgic_v3_read_iar+0x158>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd950 0xd97c (DW_OP_fbreg -0x20) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd950 0xd97c (DW_OP_fbreg -0x24) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xd950 0xd97c (DW_OP_breg31 0x30) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │ │ ││ │
│ │ │ ││ │ __vgic_v3_read_iar:659.2 (vgic-v3-sr.c) Sbepe ║return;
~ │ │ │┌─┼└>└>0000d97c: 14000014 b d9cc <__vgic_v3_read_iar+0x1a8> <- 0000d958(b.cc)<__vgic_v3_read_iar+0x158>,0000d978(b)<__vgic_v3_read_iar+0x158>
│ │ ││ │
│ │ ││ │ __vgic_v3_read_iar:662.15 (vgic-v3-sr.c) Sbepe vcpu_set_reg(║vcpu, rt, ICC_IAR1_EL1_SPURIOUS);
~ └>└>└┼>└───>0000d980: f94017e8 ldr x8, [sp, #40] <- 0000d868(b)<__vgic_v3_read_iar+0x15c>,0000d884(b)<__vgic_v3_read_iar+0x15c>,0000d8b4(b)<__vgic_v3_read_iar+0x15c>,0000d8e4(b)<__vgic_v3_read_iar+0x15c>
│ __vgic_v3_read_iar:662.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, ICC_IAR1_EL1_SPURIOUS);
~ │ 0000d984: b94023e9 ldr w9, [sp, #32]
~ │ 0000d988: f81f83a8 stur x8, [x29, #-8]
~ │ 0000d98c: 381f43a9 sturb w9, [x29, #-12]
~ │ 0000d990: 52807fe9 mov w9, #0x3ff // #1023
~ │ 0000d994: 2a0903e8 mov w8, w9
~ │ 0000d998: f81e83a8 stur x8, [x29, #-24]
q: 0xd99c 0xd9c8 vcpu_set_reg inlined from __vgic_v3_read_iar:662 (vgic-v3-sr.c) <a88ca>:
q │ vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd99c 0xd9c8 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd99c 0xd9c8 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xd99c 0xd9c8 (DW_OP_fbreg -0x18) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~q │ 0000d99c: 385f43a9 ldurb w9, [x29, #-12]
q │ vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~q │ 0000d9a0: 71007d29 subs w9, w9, #0x1f
~q │┌─────0000d9a4: 54000120 b.eq d9c8 <__vgic_v3_read_iar+0x1a4> // b.none
││
~q ││ ┌─0000d9a8: 14000001 b d9ac <__vgic_v3_read_iar+0x188> <- 0000d9a4(b.cc-succ)<fallthrough>
││ │
q ││ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~q ││ └>0000d9ac: f85e83a8 ldur x8, [x29, #-24] <- 0000d9a8(b)<__vgic_v3_read_iar+0x188>
q ││ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~q ││ 0000d9b0: f85f83a9 ldur x9, [x29, #-8]
q ││ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~q ││ 0000d9b4: 385f43aa ldurb w10, [x29, #-12]
~q ││ 0000d9b8: 2a0a03eb mov w11, w10
q ││ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~q ││ 0000d9bc: 8b0b0d29 add x9, x9, x11, lsl #3
q ││ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~q ││ 0000d9c0: f900b128 str x8, [x9, #352]
q ││ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~q ││ ┌─0000d9c4: 14000001 b d9c8 <__vgic_v3_read_iar+0x1a4>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd99c 0xd9c8 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd99c 0xd9c8 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xd99c 0xd9c8 (DW_OP_fbreg -0x18) vcpu_set_reg(inlined):__vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
││ │
││ │ __vgic_v3_read_iar:663.1 (vgic-v3-sr.c) Sbepe ║}
~ │└>┌─└>0000d9c8: 14000001 b d9cc <__vgic_v3_read_iar+0x1a8> <- 0000d9a4(b.cc)<__vgic_v3_read_iar+0x1a4>,0000d9c4(b)<__vgic_v3_read_iar+0x1a4>
│ │
~ └─>└──>0000d9cc: a9467bfd ldp x29, x30, [sp, #96] <- 0000d97c(b)<__vgic_v3_read_iar+0x1a8>,0000d9c8(b)<__vgic_v3_read_iar+0x1a8>
~ 0000d9d0: 9101c3ff add sp, sp, #0x70
0000d830 CFA:r29+16 r29:c-16 r30:c-8
~ 0000d9d4: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd824 0xd9d8 (DW_OP_breg31 0x28) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:629
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd824 0xd9d8 (DW_OP_breg31 0x24) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:629
-rt param int (base type, DW_ATE_signed size:4) 0xd824 0xd9d8 (DW_OP_breg31 0x20) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:629
-lr_val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd824 0xd9d8 (DW_OP_breg31 0x18) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:631
-lr_prio var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd824 0xd9d8 (DW_OP_breg31 0x14) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:632
-pmr var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd824 0xd9d8 (DW_OP_breg31 0x10) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:632
-lr var int (base type, DW_ATE_signed size:4) 0xd824 0xd9d8 (DW_OP_breg31 0xc) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:633
-grp var int (base type, DW_ATE_signed size:4) 0xd824 0xd9d8 (DW_OP_breg31 0x8) __vgic_v3_read_iar:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:633
**0000d9d8 <__vgic_v3_write_eoir>:
+ __vgic_v3_write_eoir params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd9d8 0xdb08 (DW_OP_fbreg -0x18)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd9d8 0xdb08 (DW_OP_fbreg -0x1c)
+rt param int (base type, DW_ATE_signed size:4) 0xd9d8 0xdb08 (DW_OP_fbreg -0x20)
__vgic_v3_write_eoir:711.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd9d8 0xdb08 (DW_OP_fbreg -0x18) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:710
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd9d8 0xdb08 (DW_OP_fbreg -0x1c) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:710
+rt param int (base type, DW_ATE_signed size:4) 0xd9d8 0xdb08 (DW_OP_fbreg -0x20) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:710
+vid var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd9d8 0xdb08 (DW_OP_fbreg -0x24) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:712
+lr_val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd9d8 0xdb08 (DW_OP_breg31 0x20) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:713
+lr_prio var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd9d8 0xdb08 (DW_OP_breg31 0x1c) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:714
+act_prio var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd9d8 0xdb08 (DW_OP_breg31 0x18) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:714
+lr var int (base type, DW_ATE_signed size:4) 0xd9d8 0xdb08 (DW_OP_breg31 0x14) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:715
+grp var int (base type, DW_ATE_signed size:4) 0xd9d8 0xdb08 (DW_OP_breg31 0x10) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:715
~ 0000d9d8: d10183ff sub sp, sp, #0x60
~ 0000d9dc: a9057bfd stp x29, x30, [sp, #80]
0000d9d8 CFA:r31 r29:u r30:u
~ 0000d9e0: 910143fd add x29, sp, #0x50
~ 0000d9e4: f81e83a0 stur x0, [x29, #-24]
~ 0000d9e8: b81e43a1 stur w1, [x29, #-28]
~ 0000d9ec: b81e03a2 stur w2, [x29, #-32]
__vgic_v3_write_eoir:712.25 (vgic-v3-sr.c) SbePe u32 vid = vcpu_get_reg(║vcpu, rt);
~ 0000d9f0: f85e83a8 ldur x8, [x29, #-24]
__vgic_v3_write_eoir:712.31 (vgic-v3-sr.c) sbepe u32 vid = vcpu_get_reg(vcpu, ║rt);
~ 0000d9f4: b85e03a9 ldur w9, [x29, #-32]
~ 0000d9f8: f81f83a8 stur x8, [x29, #-8]
~ 0000d9fc: 381f43a9 sturb w9, [x29, #-12]
r: 0xda00 0xda38 vcpu_get_reg inlined from __vgic_v3_write_eoir:712 (vgic-v3-sr.c) <a89b9>:
r vcpu_get_reg:166.10 (kvm_emulate.h) Sbepe return (║reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xda00 0xda38 (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xda00 0xda38 (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~r 0000da00: 385f43a9 ldurb w9, [x29, #-12]
r vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~r 0000da04: 71007d29 subs w9, w9, #0x1f
~r ┌──0000da08: 540000a1 b.ne da1c <__vgic_v3_write_eoir+0x44> // b.any
│
~r │┌─0000da0c: 14000001 b da10 <__vgic_v3_write_eoir+0x38> <- 0000da08(b.cc-succ)<fallthrough>
││
~r │└>0000da10: aa1f03e0 mov x0, xzr <- 0000da0c(b)<__vgic_v3_write_eoir+0x38>
~r │ 0000da14: f90007e0 str x0, [sp, #8]
r │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~r ┌┼──0000da18: 14000008 b da38 <__vgic_v3_write_eoir+0x60>
││
r ││ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~r │└─>0000da1c: f85f83a8 ldur x8, [x29, #-8] <- 0000da08(b.cc)<__vgic_v3_write_eoir+0x44>
r │ vcpu_get_reg:166.56 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[║reg_num];
~r │ 0000da20: 385f43a9 ldurb w9, [x29, #-12]
~r │ 0000da24: 2a0903ea mov w10, w9
r │ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~r │ 0000da28: 8b0a0d08 add x8, x8, x10, lsl #3
~r │ 0000da2c: f940b108 ldr x8, [x8, #352]
~r │ 0000da30: f90007e8 str x8, [sp, #8]
r │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~r │ ┌─0000da34: 14000001 b da38 <__vgic_v3_write_eoir+0x60>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xda00 0xda38 (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xda00 0xda38 (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
~ └>└>0000da38: f94007e0 ldr x0, [sp, #8] <- 0000da18(b)<__vgic_v3_write_eoir+0x60>,0000da34(b)<__vgic_v3_write_eoir+0x60>
__vgic_v3_write_eoir:712.6 (vgic-v3-sr.c) Sbepe u32 ║vid = vcpu_get_reg(vcpu, rt);
~ 0000da3c: b81dc3a0 stur w0, [x29, #-36]
__vgic_v3_write_eoir:717.28 (vgic-v3-sr.c) Sbepe grp = __vgic_v3_get_group(║vcpu);
~ 0000da40: f85e83a0 ldur x0, [x29, #-24]
__vgic_v3_write_eoir:717.8 (vgic-v3-sr.c) sbepe grp = ║__vgic_v3_get_group(vcpu);
~ 0000da44: 94000345 bl e758 <__vgic_v3_get_group>
__vgic_v3_write_eoir:717.6 (vgic-v3-sr.c) sbepe grp ║= __vgic_v3_get_group(vcpu);
~ 0000da48: b90013e0 str w0, [sp, #16] <- 0000da44(bl-succ)<return>
__vgic_v3_write_eoir:720.13 (vgic-v3-sr.c) Sbepe act_prio = ║__vgic_v3_clear_highest_active_priority();
~ 0000da4c: 94000458 bl ebac <__vgic_v3_clear_highest_active_priority>
__vgic_v3_write_eoir:720.11 (vgic-v3-sr.c) sbepe act_prio ║= __vgic_v3_clear_highest_active_priority();
~ 0000da50: 390063e0 strb w0, [sp, #24] <- 0000da4c(bl-succ)<return>
__vgic_v3_write_eoir:723.6 (vgic-v3-sr.c) Sbepe if (║vid >= VGIC_MIN_LPI)
~ 0000da54: b85dc3a8 ldur w8, [x29, #-36]
__vgic_v3_write_eoir:723.6 (vgic-v3-sr.c) sbepe if (║vid >= VGIC_MIN_LPI)
~ 0000da58: 71400908 subs w8, w8, #0x2, lsl #12
~ ┌──0000da5c: 54000063 b.cc da68 <__vgic_v3_write_eoir+0x90> // b.lo, b.ul, b.last
│
~ │┌─0000da60: 14000001 b da64 <__vgic_v3_write_eoir+0x8c> <- 0000da5c(b.cc-succ)<fallthrough>
││
││ __vgic_v3_write_eoir:724.3 (vgic-v3-sr.c) Sbepe ║return;
~ ┌───────┼└>0000da64: 14000026 b dafc <__vgic_v3_write_eoir+0x124> <- 0000da60(b)<__vgic_v3_write_eoir+0x8c>
│ │
│ │ __vgic_v3_write_eoir:727.6 (vgic-v3-sr.c) Sbepe if (║vmcr & ICH_VMCR_EOIM_MASK)
~ │ └─>0000da68: 385e53a8 ldurb w8, [x29, #-27] <- 0000da5c(b.cc)<__vgic_v3_write_eoir+0x90>
~ │ ┌──0000da6c: 36080068 tbz w8, #1, da78 <__vgic_v3_write_eoir+0xa0>
│ │
~ │ │┌─0000da70: 14000001 b da74 <__vgic_v3_write_eoir+0x9c> <- 0000da6c(b.cc-succ)<fallthrough>
│ ││
│ ││ __vgic_v3_write_eoir:728.3 (vgic-v3-sr.c) Sbepe ║return;
~ │ ┌─────┼└>0000da74: 14000022 b dafc <__vgic_v3_write_eoir+0x124> <- 0000da70(b)<__vgic_v3_write_eoir+0x9c>
│ │ │
│ │ │ __vgic_v3_write_eoir:730.32 (vgic-v3-sr.c) Sbepe lr = __vgic_v3_find_active_lr(║vcpu, vid, &lr_val);
~ │ │ └─>0000da78: f85e83a0 ldur x0, [x29, #-24] <- 0000da6c(b.cc)<__vgic_v3_write_eoir+0xa0>
│ │ __vgic_v3_write_eoir:730.38 (vgic-v3-sr.c) sbepe lr = __vgic_v3_find_active_lr(vcpu, ║vid, &lr_val);
~ │ │ 0000da7c: b85dc3a1 ldur w1, [x29, #-36]
~ │ │ 0000da80: 910083e2 add x2, sp, #0x20
│ │ __vgic_v3_write_eoir:730.7 (vgic-v3-sr.c) sbepe lr = ║__vgic_v3_find_active_lr(vcpu, vid, &lr_val);
~ │ │ 0000da84: 940004cb bl edb0 <__vgic_v3_find_active_lr>
│ │
│ │ __vgic_v3_write_eoir:730.5 (vgic-v3-sr.c) sbepe lr ║= __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
~ │ │ 0000da88: b90017e0 str w0, [sp, #20] <- 0000da84(bl-succ)<return>
│ │ __vgic_v3_write_eoir:731.6 (vgic-v3-sr.c) Sbepe if (║lr == -1) {
~ │ │ 0000da8c: b94017e8 ldr w8, [sp, #20]
│ │ __vgic_v3_write_eoir:731.6 (vgic-v3-sr.c) sbepe if (║lr == -1) {
~ │ │ 0000da90: 31000508 adds w8, w8, #0x1
~ │ │ ┌──0000da94: 54000081 b.ne daa4 <__vgic_v3_write_eoir+0xcc> // b.any
│ │ │
~ │ │ │┌─0000da98: 14000001 b da9c <__vgic_v3_write_eoir+0xc4> <- 0000da94(b.cc-succ)<fallthrough>
│ │ ││
│ │ ││ __vgic_v3_write_eoir:732.3 (vgic-v3-sr.c) Sbepe ║__vgic_v3_bump_eoicount();
~ │ │ │└>0000da9c: 940004f8 bl ee7c <__vgic_v3_bump_eoicount> <- 0000da98(b)<__vgic_v3_write_eoir+0xc4>
│ │ │
│ │ │ __vgic_v3_write_eoir:733.3 (vgic-v3-sr.c) Sbepe ║return;
~ │ │ ┌───┼──0000daa0: 14000017 b dafc <__vgic_v3_write_eoir+0x124> <- 0000da9c(bl-succ)<return>
│ │ │ │
│ │ │ │ __vgic_v3_write_eoir:736.13 (vgic-v3-sr.c) Sbepe lr_prio = (║lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
~ │ │ │ └─>0000daa4: 79404fe8 ldrh w8, [sp, #38] <- 0000da94(b.cc)<__vgic_v3_write_eoir+0xcc>
~ │ │ │ 0000daa8: 2a0803e0 mov w0, w8
│ │ │ __vgic_v3_write_eoir:736.10 (vgic-v3-sr.c) sbepe lr_prio ║= (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
~ │ │ │ 0000daac: 390073e0 strb w0, [sp, #28]
│ │ │ __vgic_v3_write_eoir:739.6 (vgic-v3-sr.c) Sbepe if (║grp != !!(lr_val & ICH_LR_GROUP) ||
~ │ │ │ 0000dab0: b94013e8 ldr w8, [sp, #16]
│ │ │ __vgic_v3_write_eoir:739.14 (vgic-v3-sr.c) sbepe if (grp != !║!(lr_val & ICH_LR_GROUP) ||
~ │ │ │ 0000dab4: 39409fe9 ldrb w9, [sp, #39]
~ │ │ │ 0000dab8: 121c0129 and w9, w9, #0x10
│ │ │ __vgic_v3_write_eoir:739.39 (vgic-v3-sr.c) sbepe if (grp != !!(lr_val & ICH_LR_GROUP) ||
~ │ │ │ 0000dabc: 6b491108 subs w8, w8, w9, lsr #4
~ │ │ │┌─────0000dac0: 54000141 b.ne dae8 <__vgic_v3_write_eoir+0x110> // b.any
│ │ ││
~ │ │ ││ ┌─0000dac4: 14000001 b dac8 <__vgic_v3_write_eoir+0xf0> <- 0000dac0(b.cc-succ)<fallthrough>
│ │ ││ │
│ │ ││ │ __vgic_v3_write_eoir:740.36 (vgic-v3-sr.c) Sbepe __vgic_v3_pri_to_pre(lr_prio, ║vmcr, grp) != act_prio)
~ │ │ ││ └>0000dac8: b85e43a1 ldur w1, [x29, #-28] <- 0000dac4(b)<__vgic_v3_write_eoir+0xf0>
│ │ ││ __vgic_v3_write_eoir:740.42 (vgic-v3-sr.c) sbepe __vgic_v3_pri_to_pre(lr_prio, vmcr, ║grp) != act_prio)
~ │ │ ││ 0000dacc: b94013e2 ldr w2, [sp, #16]
│ │ ││ __vgic_v3_write_eoir:740.6 (vgic-v3-sr.c) sbepe ║__vgic_v3_pri_to_pre(lr_prio, vmcr, grp) != act_prio)
~ │ │ ││ 0000dad0: 394073e0 ldrb w0, [sp, #28]
~ │ │ ││ 0000dad4: 940003bf bl e9d0 <__vgic_v3_pri_to_pre>
│ │ ││
│ │ ││ __vgic_v3_write_eoir:740.50 (vgic-v3-sr.c) sbepe __vgic_v3_pri_to_pre(lr_prio, vmcr, grp) != ║act_prio)
~ │ │ ││ 0000dad8: 394063e8 ldrb w8, [sp, #24] <- 0000dad4(bl-succ)<return>
│ │ ││ __vgic_v3_write_eoir:739.6 (vgic-v3-sr.c) Sbepe if (║grp != !!(lr_val & ICH_LR_GROUP) ||
~ │ │ ││ 0000dadc: 6b200108 subs w8, w8, w0, uxtb
~ │ │ ││ ┌──0000dae0: 54000060 b.eq daec <__vgic_v3_write_eoir+0x114> // b.none
│ │ ││ │
~ │ │ ││ │┌─0000dae4: 14000001 b dae8 <__vgic_v3_write_eoir+0x110> <- 0000dae0(b.cc-succ)<fallthrough>
│ │ ││ ││
│ │ ││ ││ __vgic_v3_write_eoir:741.3 (vgic-v3-sr.c) Sbepe ║return;
~ │ │ │└>┌┼└>0000dae8: 14000005 b dafc <__vgic_v3_write_eoir+0x124> <- 0000dac0(b.cc)<__vgic_v3_write_eoir+0x110>,0000dae4(b)<__vgic_v3_write_eoir+0x110>
│ │ │ ││
│ │ │ ││ __vgic_v3_write_eoir:744.28 (vgic-v3-sr.c) Sbepe __vgic_v3_clear_active_lr(║lr, lr_val);
~ │ │ │ │└─>0000daec: b94017e0 ldr w0, [sp, #20] <- 0000dae0(b.cc)<__vgic_v3_write_eoir+0x114>
│ │ │ │ __vgic_v3_write_eoir:744.32 (vgic-v3-sr.c) sbepe __vgic_v3_clear_active_lr(lr, ║lr_val);
~ │ │ │ │ 0000daf0: f94013e1 ldr x1, [sp, #32]
│ │ │ │ __vgic_v3_write_eoir:744.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_clear_active_lr(lr, lr_val);
~ │ │ │ │ 0000daf4: 940004f6 bl eecc <__vgic_v3_clear_active_lr>
│ │ │ │
│ │ │ │ __vgic_v3_write_eoir:745.1 (vgic-v3-sr.c) Sbepe ║}
~ │ │ │ │ ┌─0000daf8: 14000001 b dafc <__vgic_v3_write_eoir+0x124> <- 0000daf4(bl-succ)<return>
│ │ │ │ │
~ └>└>└─>└>└>0000dafc: a9457bfd ldp x29, x30, [sp, #80] <- 0000da64(b)<__vgic_v3_write_eoir+0x124>,0000da74(b)<__vgic_v3_write_eoir+0x124>,0000daa0(b)<__vgic_v3_write_eoir+0x124>,0000dae8(b)<__vgic_v3_write_eoir+0x124>,0000daf8(b)<__vgic_v3_write_eoir+0x124>
~ 0000db00: 910183ff add sp, sp, #0x60
0000d9e4 CFA:r29+16 r29:c-16 r30:c-8
~ 0000db04: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xd9d8 0xdb08 (DW_OP_fbreg -0x18) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:710
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd9d8 0xdb08 (DW_OP_fbreg -0x1c) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:710
-rt param int (base type, DW_ATE_signed size:4) 0xd9d8 0xdb08 (DW_OP_fbreg -0x20) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:710
-vid var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xd9d8 0xdb08 (DW_OP_fbreg -0x24) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:712
-lr_val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xd9d8 0xdb08 (DW_OP_breg31 0x20) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:713
-lr_prio var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd9d8 0xdb08 (DW_OP_breg31 0x1c) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:714
-act_prio var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xd9d8 0xdb08 (DW_OP_breg31 0x18) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:714
-lr var int (base type, DW_ATE_signed size:4) 0xd9d8 0xdb08 (DW_OP_breg31 0x14) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:715
-grp var int (base type, DW_ATE_signed size:4) 0xd9d8 0xdb08 (DW_OP_breg31 0x10) __vgic_v3_write_eoir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:715
**0000db08 <__vgic_v3_read_igrpen1>:
+ __vgic_v3_read_igrpen1 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdb08 0xdb6c (DW_OP_fbreg 0x10)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdb08 0xdb6c (DW_OP_fbreg 0xc)
+rt param int (base type, DW_ATE_signed size:4) 0xdb08 0xdb6c (DW_OP_fbreg 0x8)
__vgic_v3_read_igrpen1:753.0 (vgic-v3-sr.c) Sbepe ║{
0000db08 CFA:r31
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdb08 0xdb6c (DW_OP_fbreg 0x10) __vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:752
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdb08 0xdb6c (DW_OP_fbreg 0xc) __vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:752
+rt param int (base type, DW_ATE_signed size:4) 0xdb08 0xdb6c (DW_OP_fbreg 0x8) __vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:752
~ 0000db08: d100c3ff sub sp, sp, #0x30
~ 0000db0c: f9000be0 str x0, [sp, #16]
~ 0000db10: b9000fe1 str w1, [sp, #12]
~ 0000db14: b9000be2 str w2, [sp, #8]
__vgic_v3_read_igrpen1:754.15 (vgic-v3-sr.c) SbePe vcpu_set_reg(║vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
~ 0000db18: f9400be8 ldr x8, [sp, #16]
__vgic_v3_read_igrpen1:754.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
~ 0000db1c: b9400be9 ldr w9, [sp, #8]
__vgic_v3_read_igrpen1:754.28 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, !!(║vmcr & ICH_VMCR_ENG1_MASK));
~ 0000db20: b9400fea ldr w10, [sp, #12]
__vgic_v3_read_igrpen1:754.26 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, !║!(vmcr & ICH_VMCR_ENG1_MASK));
~ 0000db24: 5301054a ubfx w10, w10, #1, #1
__vgic_v3_read_igrpen1:754.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║!!(vmcr & ICH_VMCR_ENG1_MASK));
~ 0000db28: 2a0a03eb mov w11, w10
~ 0000db2c: f90017e8 str x8, [sp, #40]
~ 0000db30: 390093e9 strb w9, [sp, #36]
~ 0000db34: f9000feb str x11, [sp, #24]
s: 0xdb38 0xdb64 vcpu_set_reg inlined from __vgic_v3_read_igrpen1:754 (vgic-v3-sr.c) <a8a23>:
s vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdb38 0xdb64 (DW_OP_fbreg 0x28) vcpu_set_reg(inlined):__vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdb38 0xdb64 (DW_OP_fbreg 0x24) vcpu_set_reg(inlined):__vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xdb38 0xdb64 (DW_OP_fbreg 0x18) vcpu_set_reg(inlined):__vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~s 0000db38: 394093e9 ldrb w9, [sp, #36]
s vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~s 0000db3c: 71007d29 subs w9, w9, #0x1f
~s ┌───0000db40: 54000120 b.eq db64 <__vgic_v3_read_igrpen1+0x5c> // b.none
│
~s │ ┌─0000db44: 14000001 b db48 <__vgic_v3_read_igrpen1+0x40> <- 0000db40(b.cc-succ)<fallthrough>
│ │
s │ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~s │ └>0000db48: f9400fe8 ldr x8, [sp, #24] <- 0000db44(b)<__vgic_v3_read_igrpen1+0x40>
s │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~s │ 0000db4c: f94017e9 ldr x9, [sp, #40]
s │ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~s │ 0000db50: 394093ea ldrb w10, [sp, #36]
~s │ 0000db54: 2a0a03eb mov w11, w10
s │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~s │ 0000db58: 8b0b0d29 add x9, x9, x11, lsl #3
s │ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~s │ 0000db5c: f900b128 str x8, [x9, #352]
s │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~s │ ┌─0000db60: 14000001 b db64 <__vgic_v3_read_igrpen1+0x5c>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdb38 0xdb64 (DW_OP_fbreg 0x28) vcpu_set_reg(inlined):__vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdb38 0xdb64 (DW_OP_fbreg 0x24) vcpu_set_reg(inlined):__vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xdb38 0xdb64 (DW_OP_fbreg 0x18) vcpu_set_reg(inlined):__vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
│ │ __vgic_v3_read_igrpen1:755.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000db64: 9100c3ff add sp, sp, #0x30 <- 0000db40(b.cc)<__vgic_v3_read_igrpen1+0x5c>,0000db60(b)<__vgic_v3_read_igrpen1+0x5c>
0000db0c CFA:r31+48
~ 0000db68: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdb08 0xdb6c (DW_OP_fbreg 0x10) __vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:752
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdb08 0xdb6c (DW_OP_fbreg 0xc) __vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:752
-rt param int (base type, DW_ATE_signed size:4) 0xdb08 0xdb6c (DW_OP_fbreg 0x8) __vgic_v3_read_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:752
**0000db6c <__vgic_v3_write_igrpen1>:
+ __vgic_v3_write_igrpen1 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdb6c 0xdc14 (DW_OP_breg31 0x18)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdb6c 0xdc14 (DW_OP_breg31 0x14)
+rt param int (base type, DW_ATE_signed size:4) 0xdb6c 0xdc14 (DW_OP_breg31 0x10)
__vgic_v3_write_igrpen1:770.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdb6c 0xdc14 (DW_OP_breg31 0x18) __vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:769
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdb6c 0xdc14 (DW_OP_breg31 0x14) __vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:769
+rt param int (base type, DW_ATE_signed size:4) 0xdb6c 0xdc14 (DW_OP_breg31 0x10) __vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:769
+val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xdb6c 0xdc14 (DW_OP_breg31 0x8) __vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:771
~ 0000db6c: d10103ff sub sp, sp, #0x40
~ 0000db70: a9037bfd stp x29, x30, [sp, #48]
0000db6c CFA:r31 r29:u r30:u
~ 0000db74: 9100c3fd add x29, sp, #0x30
~ 0000db78: f9000fe0 str x0, [sp, #24]
~ 0000db7c: b90017e1 str w1, [sp, #20]
~ 0000db80: b90013e2 str w2, [sp, #16]
__vgic_v3_write_igrpen1:771.25 (vgic-v3-sr.c) SbePe u64 val = vcpu_get_reg(║vcpu, rt);
~ 0000db84: f9400fe8 ldr x8, [sp, #24]
__vgic_v3_write_igrpen1:771.31 (vgic-v3-sr.c) sbepe u64 val = vcpu_get_reg(vcpu, ║rt);
~ 0000db88: b94013e9 ldr w9, [sp, #16]
~ 0000db8c: f81f83a8 stur x8, [x29, #-8]
~ 0000db90: 381f43a9 sturb w9, [x29, #-12]
t: 0xdb94 0xdbcc vcpu_get_reg inlined from __vgic_v3_write_igrpen1:771 (vgic-v3-sr.c) <a8aa4>:
t vcpu_get_reg:166.10 (kvm_emulate.h) Sbepe return (║reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xdb94 0xdbcc (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdb94 0xdbcc (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~t 0000db94: 385f43a9 ldurb w9, [x29, #-12]
t vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~t 0000db98: 71007d29 subs w9, w9, #0x1f
~t ┌──0000db9c: 540000a1 b.ne dbb0 <__vgic_v3_write_igrpen1+0x44> // b.any
│
~t │┌─0000dba0: 14000001 b dba4 <__vgic_v3_write_igrpen1+0x38> <- 0000db9c(b.cc-succ)<fallthrough>
││
~t │└>0000dba4: aa1f03e0 mov x0, xzr <- 0000dba0(b)<__vgic_v3_write_igrpen1+0x38>
~t │ 0000dba8: f90003e0 str x0, [sp]
t │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~t ┌┼──0000dbac: 14000008 b dbcc <__vgic_v3_write_igrpen1+0x60>
││
t ││ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~t │└─>0000dbb0: f85f83a8 ldur x8, [x29, #-8] <- 0000db9c(b.cc)<__vgic_v3_write_igrpen1+0x44>
t │ vcpu_get_reg:166.56 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[║reg_num];
~t │ 0000dbb4: 385f43a9 ldurb w9, [x29, #-12]
~t │ 0000dbb8: 2a0903ea mov w10, w9
t │ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~t │ 0000dbbc: 8b0a0d08 add x8, x8, x10, lsl #3
~t │ 0000dbc0: f940b108 ldr x8, [x8, #352]
~t │ 0000dbc4: f90003e8 str x8, [sp]
t │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~t │ ┌─0000dbc8: 14000001 b dbcc <__vgic_v3_write_igrpen1+0x60>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xdb94 0xdbcc (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdb94 0xdbcc (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
~ └>└>0000dbcc: f94003e8 ldr x8, [sp] <- 0000dbac(b)<__vgic_v3_write_igrpen1+0x60>,0000dbc8(b)<__vgic_v3_write_igrpen1+0x60>
__vgic_v3_write_igrpen1:771.6 (vgic-v3-sr.c) Sbepe u64 ║val = vcpu_get_reg(vcpu, rt);
~ 0000dbd0: f90007e8 str x8, [sp, #8]
__vgic_v3_write_igrpen1:773.6 (vgic-v3-sr.c) Sbepe if (║val & 1)
~ 0000dbd4: 394023e9 ldrb w9, [sp, #8]
~ ┌──0000dbd8: 360000c9 tbz w9, #0, dbf0 <__vgic_v3_write_igrpen1+0x84>
│
~ │┌─0000dbdc: 14000001 b dbe0 <__vgic_v3_write_igrpen1+0x74> <- 0000dbd8(b.cc-succ)<fallthrough>
││
││ __vgic_v3_write_igrpen1:774.8 (vgic-v3-sr.c) Sbepe vmcr ║|= ICH_VMCR_ENG1_MASK;
~ │└>0000dbe0: b94017e8 ldr w8, [sp, #20] <- 0000dbdc(b)<__vgic_v3_write_igrpen1+0x74>
~ │ 0000dbe4: 321f0108 orr w8, w8, #0x2
~ │ 0000dbe8: b90017e8 str w8, [sp, #20]
│ __vgic_v3_write_igrpen1:774.3 (vgic-v3-sr.c) sbepe ║vmcr |= ICH_VMCR_ENG1_MASK;
~ ┌┼──0000dbec: 14000005 b dc00 <__vgic_v3_write_igrpen1+0x94>
││
││ __vgic_v3_write_igrpen1:776.8 (vgic-v3-sr.c) Sbepe vmcr ║&= ~ICH_VMCR_ENG1_MASK;
~ │└─>0000dbf0: b94017e8 ldr w8, [sp, #20] <- 0000dbd8(b.cc)<__vgic_v3_write_igrpen1+0x84>
~ │ 0000dbf4: 121e7908 and w8, w8, #0xfffffffd
~ │ 0000dbf8: b90017e8 str w8, [sp, #20]
~ │ ┌─0000dbfc: 14000001 b dc00 <__vgic_v3_write_igrpen1+0x94>
│ │
│ │ __vgic_v3_write_igrpen1:778.23 (vgic-v3-sr.c) Sbepe __vgic_v3_write_vmcr(║vmcr);
~ └>└>0000dc00: b94017e0 ldr w0, [sp, #20] <- 0000dbec(b)<__vgic_v3_write_igrpen1+0x94>,0000dbfc(b)<__vgic_v3_write_igrpen1+0x94>
__vgic_v3_write_igrpen1:778.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_vmcr(vmcr);
~ 0000dc04: 97fffd38 bl d0e4 <__vgic_v3_write_vmcr>
__vgic_v3_write_igrpen1:779.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000dc08: a9437bfd ldp x29, x30, [sp, #48] <- 0000dc04(bl-succ)<return>
~ 0000dc0c: 910103ff add sp, sp, #0x40
0000db78 CFA:r29+16 r29:c-16 r30:c-8
~ 0000dc10: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdb6c 0xdc14 (DW_OP_breg31 0x18) __vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:769
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdb6c 0xdc14 (DW_OP_breg31 0x14) __vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:769
-rt param int (base type, DW_ATE_signed size:4) 0xdb6c 0xdc14 (DW_OP_breg31 0x10) __vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:769
-val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xdb6c 0xdc14 (DW_OP_breg31 0x8) __vgic_v3_write_igrpen1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:771
**0000dc14 <__vgic_v3_read_bpr1>:
+ __vgic_v3_read_bpr1 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdc14 0xdc98 (DW_OP_breg31 0x20)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdc14 0xdc98 (DW_OP_breg31 0x1c)
+rt param int (base type, DW_ATE_signed size:4) 0xdc14 0xdc98 (DW_OP_breg31 0x18)
__vgic_v3_read_bpr1:787.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdc14 0xdc98 (DW_OP_breg31 0x20) __vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:786
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdc14 0xdc98 (DW_OP_breg31 0x1c) __vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:786
+rt param int (base type, DW_ATE_signed size:4) 0xdc14 0xdc98 (DW_OP_breg31 0x18) __vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:786
~ 0000dc14: d10143ff sub sp, sp, #0x50
~ 0000dc18: a9047bfd stp x29, x30, [sp, #64]
0000dc14 CFA:r31 r29:u r30:u
~ 0000dc1c: 910103fd add x29, sp, #0x40
~ 0000dc20: f90013e0 str x0, [sp, #32]
~ 0000dc24: b9001fe1 str w1, [sp, #28]
~ 0000dc28: b9001be2 str w2, [sp, #24]
__vgic_v3_read_bpr1:788.15 (vgic-v3-sr.c) SbePe vcpu_set_reg(║vcpu, rt, __vgic_v3_get_bpr1(vmcr));
~ 0000dc2c: f94013e8 ldr x8, [sp, #32]
__vgic_v3_read_bpr1:788.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, __vgic_v3_get_bpr1(vmcr));
~ 0000dc30: b9401be9 ldr w9, [sp, #24]
__vgic_v3_read_bpr1:788.44 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(║vmcr));
~ 0000dc34: b9401fe0 ldr w0, [sp, #28]
~ 0000dc38: f9000be8 str x8, [sp, #16]
~ 0000dc3c: b9000fe9 str w9, [sp, #12]
__vgic_v3_read_bpr1:788.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║__vgic_v3_get_bpr1(vmcr));
~ 0000dc40: 940003c0 bl eb40 <__vgic_v3_get_bpr1>
~ 0000dc44: 2a0003e9 mov w9, w0 <- 0000dc40(bl-succ)<return>
~ 0000dc48: 2a0903e8 mov w8, w9
~ 0000dc4c: f9400bea ldr x10, [sp, #16]
~ 0000dc50: f81f83aa stur x10, [x29, #-8]
~ 0000dc54: b9400fe9 ldr w9, [sp, #12]
~ 0000dc58: 381f43a9 sturb w9, [x29, #-12]
~ 0000dc5c: f81e83a8 stur x8, [x29, #-24]
u: 0xdc60 0xdc8c vcpu_set_reg inlined from __vgic_v3_read_bpr1:788 (vgic-v3-sr.c) <a8b0e>:
u vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdc60 0xdc8c (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdc60 0xdc8c (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xdc60 0xdc8c (DW_OP_fbreg -0x18) vcpu_set_reg(inlined):__vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~u 0000dc60: 385f43a9 ldurb w9, [x29, #-12]
u vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~u 0000dc64: 71007d29 subs w9, w9, #0x1f
~u ┌───0000dc68: 54000120 b.eq dc8c <__vgic_v3_read_bpr1+0x78> // b.none
│
~u │ ┌─0000dc6c: 14000001 b dc70 <__vgic_v3_read_bpr1+0x5c> <- 0000dc68(b.cc-succ)<fallthrough>
│ │
u │ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~u │ └>0000dc70: f85e83a8 ldur x8, [x29, #-24] <- 0000dc6c(b)<__vgic_v3_read_bpr1+0x5c>
u │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~u │ 0000dc74: f85f83a9 ldur x9, [x29, #-8]
u │ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~u │ 0000dc78: 385f43aa ldurb w10, [x29, #-12]
~u │ 0000dc7c: 2a0a03eb mov w11, w10
u │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~u │ 0000dc80: 8b0b0d29 add x9, x9, x11, lsl #3
u │ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~u │ 0000dc84: f900b128 str x8, [x9, #352]
u │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~u │ ┌─0000dc88: 14000001 b dc8c <__vgic_v3_read_bpr1+0x78>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdc60 0xdc8c (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdc60 0xdc8c (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xdc60 0xdc8c (DW_OP_fbreg -0x18) vcpu_set_reg(inlined):__vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
│ │ __vgic_v3_read_bpr1:789.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000dc8c: a9447bfd ldp x29, x30, [sp, #64] <- 0000dc68(b.cc)<__vgic_v3_read_bpr1+0x78>,0000dc88(b)<__vgic_v3_read_bpr1+0x78>
~ 0000dc90: 910143ff add sp, sp, #0x50
0000dc20 CFA:r29+16 r29:c-16 r30:c-8
~ 0000dc94: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdc14 0xdc98 (DW_OP_breg31 0x20) __vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:786
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdc14 0xdc98 (DW_OP_breg31 0x1c) __vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:786
-rt param int (base type, DW_ATE_signed size:4) 0xdc14 0xdc98 (DW_OP_breg31 0x18) __vgic_v3_read_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:786
**0000dc98 <__vgic_v3_write_bpr1>:
+ __vgic_v3_write_bpr1 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdc98 0xdd90 (DW_OP_fbreg -0x18)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdc98 0xdd90 (DW_OP_fbreg -0x1c)
+rt param int (base type, DW_ATE_signed size:4) 0xdc98 0xdd90 (DW_OP_breg31 0x20)
__vgic_v3_write_bpr1:809.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdc98 0xdd90 (DW_OP_fbreg -0x18) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:808
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdc98 0xdd90 (DW_OP_fbreg -0x1c) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:808
+rt param int (base type, DW_ATE_signed size:4) 0xdc98 0xdd90 (DW_OP_breg31 0x20) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:808
+val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xdc98 0xdd90 (DW_OP_breg31 0x18) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:810
+bpr_min var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdc98 0xdd90 (DW_OP_breg31 0x14) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:811
~ 0000dc98: d10143ff sub sp, sp, #0x50
~ 0000dc9c: a9047bfd stp x29, x30, [sp, #64]
0000dc98 CFA:r31 r29:u r30:u
~ 0000dca0: 910103fd add x29, sp, #0x40
~ 0000dca4: f81e83a0 stur x0, [x29, #-24]
~ 0000dca8: b81e43a1 stur w1, [x29, #-28]
~ 0000dcac: b90023e2 str w2, [sp, #32]
__vgic_v3_write_bpr1:810.25 (vgic-v3-sr.c) SbePe u64 val = vcpu_get_reg(║vcpu, rt);
~ 0000dcb0: f85e83a8 ldur x8, [x29, #-24]
__vgic_v3_write_bpr1:810.31 (vgic-v3-sr.c) sbepe u64 val = vcpu_get_reg(vcpu, ║rt);
~ 0000dcb4: b94023e9 ldr w9, [sp, #32]
~ 0000dcb8: f81f83a8 stur x8, [x29, #-8]
~ 0000dcbc: 381f43a9 sturb w9, [x29, #-12]
v: 0xdcc0 0xdcf8 vcpu_get_reg inlined from __vgic_v3_write_bpr1:810 (vgic-v3-sr.c) <a8b9e>:
v vcpu_get_reg:166.10 (kvm_emulate.h) Sbepe return (║reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xdcc0 0xdcf8 (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdcc0 0xdcf8 (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~v 0000dcc0: 385f43a9 ldurb w9, [x29, #-12]
v vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~v 0000dcc4: 71007d29 subs w9, w9, #0x1f
~v ┌──0000dcc8: 540000a1 b.ne dcdc <__vgic_v3_write_bpr1+0x44> // b.any
│
~v │┌─0000dccc: 14000001 b dcd0 <__vgic_v3_write_bpr1+0x38> <- 0000dcc8(b.cc-succ)<fallthrough>
││
~v │└>0000dcd0: aa1f03e0 mov x0, xzr <- 0000dccc(b)<__vgic_v3_write_bpr1+0x38>
~v │ 0000dcd4: f90007e0 str x0, [sp, #8]
v │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~v ┌┼──0000dcd8: 14000008 b dcf8 <__vgic_v3_write_bpr1+0x60>
││
v ││ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~v │└─>0000dcdc: f85f83a8 ldur x8, [x29, #-8] <- 0000dcc8(b.cc)<__vgic_v3_write_bpr1+0x44>
v │ vcpu_get_reg:166.56 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[║reg_num];
~v │ 0000dce0: 385f43a9 ldurb w9, [x29, #-12]
~v │ 0000dce4: 2a0903ea mov w10, w9
v │ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~v │ 0000dce8: 8b0a0d08 add x8, x8, x10, lsl #3
~v │ 0000dcec: f940b108 ldr x8, [x8, #352]
~v │ 0000dcf0: f90007e8 str x8, [sp, #8]
v │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~v │ ┌─0000dcf4: 14000001 b dcf8 <__vgic_v3_write_bpr1+0x60>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xdcc0 0xdcf8 (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdcc0 0xdcf8 (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
~ └>└>0000dcf8: f94007e8 ldr x8, [sp, #8] <- 0000dcd8(b)<__vgic_v3_write_bpr1+0x60>,0000dcf4(b)<__vgic_v3_write_bpr1+0x60>
__vgic_v3_write_bpr1:810.6 (vgic-v3-sr.c) Sbepe u64 ║val = vcpu_get_reg(vcpu, rt);
~ 0000dcfc: f9000fe8 str x8, [sp, #24]
__vgic_v3_write_bpr1:811.15 (vgic-v3-sr.c) Sbepe u8 bpr_min = ║__vgic_v3_bpr_min();
~ 0000dd00: 94000380 bl eb00 <__vgic_v3_bpr_min>
__vgic_v3_write_bpr1:811.5 (vgic-v3-sr.c) sbepe u8 ║bpr_min = __vgic_v3_bpr_min();
~ 0000dd04: 390053e0 strb w0, [sp, #20] <- 0000dd00(bl-succ)<return>
__vgic_v3_write_bpr1:813.6 (vgic-v3-sr.c) Sbepe if (║vmcr & ICH_VMCR_CBPR_MASK)
~ 0000dd08: 385e43a9 ldurb w9, [x29, #-28]
~ ┌──0000dd0c: 36200069 tbz w9, #4, dd18 <__vgic_v3_write_bpr1+0x80>
│
~ │┌─0000dd10: 14000001 b dd14 <__vgic_v3_write_bpr1+0x7c> <- 0000dd0c(b.cc-succ)<fallthrough>
││
││ __vgic_v3_write_bpr1:814.3 (vgic-v3-sr.c) Sbepe ║return;
~ ┌─┼└>0000dd14: 1400001c b dd84 <__vgic_v3_write_bpr1+0xec> <- 0000dd10(b)<__vgic_v3_write_bpr1+0x7c>
│ │
│ │ __vgic_v3_write_bpr1:817.6 (vgic-v3-sr.c) Sbepe if (║val < bpr_min)
~ │ └─>0000dd18: f9400fe8 ldr x8, [sp, #24] <- 0000dd0c(b.cc)<__vgic_v3_write_bpr1+0x80>
│ __vgic_v3_write_bpr1:817.12 (vgic-v3-sr.c) sbepe if (val < ║bpr_min)
~ │ 0000dd1c: 394053e9 ldrb w9, [sp, #20]
~ │ 0000dd20: 2a0903ea mov w10, w9
│ __vgic_v3_write_bpr1:817.6 (vgic-v3-sr.c) sbepe if (║val < bpr_min)
~ │ 0000dd24: eb0a0108 subs x8, x8, x10
~ │┌───0000dd28: 540000c2 b.cs dd40 <__vgic_v3_write_bpr1+0xa8> // b.hs, b.nlast
││
~ ││ ┌─0000dd2c: 14000001 b dd30 <__vgic_v3_write_bpr1+0x98> <- 0000dd28(b.cc-succ)<fallthrough>
││ │
││ │ __vgic_v3_write_bpr1:818.9 (vgic-v3-sr.c) Sbepe val = ║bpr_min;
~ ││ └>0000dd30: 394053e8 ldrb w8, [sp, #20] <- 0000dd2c(b)<__vgic_v3_write_bpr1+0x98>
~ ││ 0000dd34: 2a0803e9 mov w9, w8
││ __vgic_v3_write_bpr1:818.7 (vgic-v3-sr.c) sbepe val ║= bpr_min;
~ ││ 0000dd38: f9000fe9 str x9, [sp, #24]
││ __vgic_v3_write_bpr1:818.3 (vgic-v3-sr.c) sbepe ║val = bpr_min;
~ ││ ┌─0000dd3c: 14000001 b dd40 <__vgic_v3_write_bpr1+0xa8>
││ │
││ │ __vgic_v3_write_bpr1:820.6 (vgic-v3-sr.c) Sbepe val ║<<= ICH_VMCR_BPR1_SHIFT;
~ │└>└>0000dd40: f9400fe8 ldr x8, [sp, #24] <- 0000dd28(b.cc)<__vgic_v3_write_bpr1+0xa8>,0000dd3c(b)<__vgic_v3_write_bpr1+0xa8>
~ │ 0000dd44: d36eb508 lsl x8, x8, #18
~ │ 0000dd48: f9000fe8 str x8, [sp, #24]
│ __vgic_v3_write_bpr1:821.6 (vgic-v3-sr.c) Sbepe val ║&= ICH_VMCR_BPR1_MASK;
~ │ 0000dd4c: f9400fe8 ldr x8, [sp, #24]
~ │ 0000dd50: 926e0908 and x8, x8, #0x1c0000
~ │ 0000dd54: f9000fe8 str x8, [sp, #24]
│ __vgic_v3_write_bpr1:822.7 (vgic-v3-sr.c) Sbepe vmcr ║&= ~ICH_VMCR_BPR1_MASK;
~ │ 0000dd58: b85e43a9 ldur w9, [x29, #-28]
~ │ 0000dd5c: 120b7129 and w9, w9, #0xffe3ffff
~ │ 0000dd60: b81e43a9 stur w9, [x29, #-28]
│ __vgic_v3_write_bpr1:823.10 (vgic-v3-sr.c) Sbepe vmcr |= ║val;
~ │ 0000dd64: b9401be9 ldr w9, [sp, #24]
│ __vgic_v3_write_bpr1:823.7 (vgic-v3-sr.c) sbepe vmcr ║|= val;
~ │ 0000dd68: b85e43aa ldur w10, [x29, #-28]
~ │ 0000dd6c: 2a090149 orr w9, w10, w9
~ │ 0000dd70: 2a0903e0 mov w0, w9
~ │ 0000dd74: b81e43a0 stur w0, [x29, #-28]
│ __vgic_v3_write_bpr1:825.23 (vgic-v3-sr.c) Sbepe __vgic_v3_write_vmcr(║vmcr);
~ │ 0000dd78: b85e43a0 ldur w0, [x29, #-28]
│ __vgic_v3_write_bpr1:825.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_vmcr(vmcr);
~ │ 0000dd7c: 97fffcda bl d0e4 <__vgic_v3_write_vmcr>
│
│ __vgic_v3_write_bpr1:826.1 (vgic-v3-sr.c) Sbepe ║}
~ │ ┌─0000dd80: 14000001 b dd84 <__vgic_v3_write_bpr1+0xec> <- 0000dd7c(bl-succ)<return>
│ │
~ └─>└>0000dd84: a9447bfd ldp x29, x30, [sp, #64] <- 0000dd14(b)<__vgic_v3_write_bpr1+0xec>,0000dd80(b)<__vgic_v3_write_bpr1+0xec>
~ 0000dd88: 910143ff add sp, sp, #0x50
0000dca4 CFA:r29+16 r29:c-16 r30:c-8
~ 0000dd8c: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdc98 0xdd90 (DW_OP_fbreg -0x18) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:808
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdc98 0xdd90 (DW_OP_fbreg -0x1c) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:808
-rt param int (base type, DW_ATE_signed size:4) 0xdc98 0xdd90 (DW_OP_breg31 0x20) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:808
-val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xdc98 0xdd90 (DW_OP_breg31 0x18) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:810
-bpr_min var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdc98 0xdd90 (DW_OP_breg31 0x14) __vgic_v3_write_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:811
**0000dd90 <__vgic_v3_read_apxr0>:
+ __vgic_v3_read_apxr0 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdd90 0xddc4 (DW_OP_breg31 0x8)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdd90 0xddc4 (DW_OP_breg31 0x4)
+rt param int (base type, DW_ATE_signed size:4) 0xdd90 0xddc4 (DW_OP_breg31 0x0)
__vgic_v3_read_apxr0:852.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdd90 0xddc4 (DW_OP_breg31 0x8) __vgic_v3_read_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:850
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdd90 0xddc4 (DW_OP_breg31 0x4) __vgic_v3_read_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:851
+rt param int (base type, DW_ATE_signed size:4) 0xdd90 0xddc4 (DW_OP_breg31 0x0) __vgic_v3_read_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:851
~ 0000dd90: d10083ff sub sp, sp, #0x20
~ 0000dd94: a9017bfd stp x29, x30, [sp, #16]
0000dd90 CFA:r31 r29:u r30:u
~ 0000dd98: 910043fd add x29, sp, #0x10
~ 0000dd9c: f90007e0 str x0, [sp, #8]
~ 0000dda0: b90007e1 str w1, [sp, #4]
~ 0000dda4: b90003e2 str w2, [sp]
__vgic_v3_read_apxr0:853.23 (vgic-v3-sr.c) SbePe __vgic_v3_read_apxrn(║vcpu, rt, 0);
~ 0000dda8: f94007e0 ldr x0, [sp, #8]
__vgic_v3_read_apxr0:853.29 (vgic-v3-sr.c) sbepe __vgic_v3_read_apxrn(vcpu, ║rt, 0);
~ 0000ddac: b94003e1 ldr w1, [sp]
~ 0000ddb0: 2a1f03e2 mov w2, wzr
__vgic_v3_read_apxr0:853.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_read_apxrn(vcpu, rt, 0);
~ 0000ddb4: 94000463 bl ef40 <__vgic_v3_read_apxrn>
__vgic_v3_read_apxr0:854.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000ddb8: a9417bfd ldp x29, x30, [sp, #16] <- 0000ddb4(bl-succ)<return>
~ 0000ddbc: 910083ff add sp, sp, #0x20
0000dd9c CFA:r29+16 r29:c-16 r30:c-8
~ 0000ddc0: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdd90 0xddc4 (DW_OP_breg31 0x8) __vgic_v3_read_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:850
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdd90 0xddc4 (DW_OP_breg31 0x4) __vgic_v3_read_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:851
-rt param int (base type, DW_ATE_signed size:4) 0xdd90 0xddc4 (DW_OP_breg31 0x0) __vgic_v3_read_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:851
**0000ddc4 <__vgic_v3_write_apxr0>:
+ __vgic_v3_write_apxr0 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xddc4 0xddf8 (DW_OP_breg31 0x8)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xddc4 0xddf8 (DW_OP_breg31 0x4)
+rt param int (base type, DW_ATE_signed size:4) 0xddc4 0xddf8 (DW_OP_breg31 0x0)
__vgic_v3_write_apxr0:873.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xddc4 0xddf8 (DW_OP_breg31 0x8) __vgic_v3_write_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:872
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xddc4 0xddf8 (DW_OP_breg31 0x4) __vgic_v3_write_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:872
+rt param int (base type, DW_ATE_signed size:4) 0xddc4 0xddf8 (DW_OP_breg31 0x0) __vgic_v3_write_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:872
~ 0000ddc4: d10083ff sub sp, sp, #0x20
~ 0000ddc8: a9017bfd stp x29, x30, [sp, #16]
0000ddc4 CFA:r31 r29:u r30:u
~ 0000ddcc: 910043fd add x29, sp, #0x10
~ 0000ddd0: f90007e0 str x0, [sp, #8]
~ 0000ddd4: b90007e1 str w1, [sp, #4]
~ 0000ddd8: b90003e2 str w2, [sp]
__vgic_v3_write_apxr0:874.24 (vgic-v3-sr.c) SbePe __vgic_v3_write_apxrn(║vcpu, rt, 0);
~ 0000dddc: f94007e0 ldr x0, [sp, #8]
__vgic_v3_write_apxr0:874.30 (vgic-v3-sr.c) sbepe __vgic_v3_write_apxrn(vcpu, ║rt, 0);
~ 0000dde0: b94003e1 ldr w1, [sp]
~ 0000dde4: 2a1f03e2 mov w2, wzr
__vgic_v3_write_apxr0:874.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_apxrn(vcpu, rt, 0);
~ 0000dde8: 9400047d bl efdc <__vgic_v3_write_apxrn>
__vgic_v3_write_apxr0:875.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000ddec: a9417bfd ldp x29, x30, [sp, #16] <- 0000dde8(bl-succ)<return>
~ 0000ddf0: 910083ff add sp, sp, #0x20
0000ddd0 CFA:r29+16 r29:c-16 r30:c-8
~ 0000ddf4: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xddc4 0xddf8 (DW_OP_breg31 0x8) __vgic_v3_write_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:872
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xddc4 0xddf8 (DW_OP_breg31 0x4) __vgic_v3_write_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:872
-rt param int (base type, DW_ATE_signed size:4) 0xddc4 0xddf8 (DW_OP_breg31 0x0) __vgic_v3_write_apxr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:872
**0000ddf8 <__vgic_v3_read_apxr1>:
+ __vgic_v3_read_apxr1 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xddf8 0xde2c (DW_OP_breg31 0x8)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xddf8 0xde2c (DW_OP_breg31 0x4)
+rt param int (base type, DW_ATE_signed size:4) 0xddf8 0xde2c (DW_OP_breg31 0x0)
__vgic_v3_read_apxr1:858.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xddf8 0xde2c (DW_OP_breg31 0x8) __vgic_v3_read_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:856
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xddf8 0xde2c (DW_OP_breg31 0x4) __vgic_v3_read_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:857
+rt param int (base type, DW_ATE_signed size:4) 0xddf8 0xde2c (DW_OP_breg31 0x0) __vgic_v3_read_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:857
~ 0000ddf8: d10083ff sub sp, sp, #0x20
~ 0000ddfc: a9017bfd stp x29, x30, [sp, #16]
0000ddf8 CFA:r31 r29:u r30:u
~ 0000de00: 910043fd add x29, sp, #0x10
~ 0000de04: f90007e0 str x0, [sp, #8]
~ 0000de08: b90007e1 str w1, [sp, #4]
~ 0000de0c: b90003e2 str w2, [sp]
__vgic_v3_read_apxr1:859.23 (vgic-v3-sr.c) SbePe __vgic_v3_read_apxrn(║vcpu, rt, 1);
~ 0000de10: f94007e0 ldr x0, [sp, #8]
__vgic_v3_read_apxr1:859.29 (vgic-v3-sr.c) sbepe __vgic_v3_read_apxrn(vcpu, ║rt, 1);
~ 0000de14: b94003e1 ldr w1, [sp]
~ 0000de18: 52800022 mov w2, #0x1 // #1
__vgic_v3_read_apxr1:859.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_read_apxrn(vcpu, rt, 1);
~ 0000de1c: 94000449 bl ef40 <__vgic_v3_read_apxrn>
__vgic_v3_read_apxr1:860.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000de20: a9417bfd ldp x29, x30, [sp, #16] <- 0000de1c(bl-succ)<return>
~ 0000de24: 910083ff add sp, sp, #0x20
0000de04 CFA:r29+16 r29:c-16 r30:c-8
~ 0000de28: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xddf8 0xde2c (DW_OP_breg31 0x8) __vgic_v3_read_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:856
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xddf8 0xde2c (DW_OP_breg31 0x4) __vgic_v3_read_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:857
-rt param int (base type, DW_ATE_signed size:4) 0xddf8 0xde2c (DW_OP_breg31 0x0) __vgic_v3_read_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:857
**0000de2c <__vgic_v3_write_apxr1>:
+ __vgic_v3_write_apxr1 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xde2c 0xde60 (DW_OP_breg31 0x8)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xde2c 0xde60 (DW_OP_breg31 0x4)
+rt param int (base type, DW_ATE_signed size:4) 0xde2c 0xde60 (DW_OP_breg31 0x0)
__vgic_v3_write_apxr1:878.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xde2c 0xde60 (DW_OP_breg31 0x8) __vgic_v3_write_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:877
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xde2c 0xde60 (DW_OP_breg31 0x4) __vgic_v3_write_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:877
+rt param int (base type, DW_ATE_signed size:4) 0xde2c 0xde60 (DW_OP_breg31 0x0) __vgic_v3_write_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:877
~ 0000de2c: d10083ff sub sp, sp, #0x20
~ 0000de30: a9017bfd stp x29, x30, [sp, #16]
0000de2c CFA:r31 r29:u r30:u
~ 0000de34: 910043fd add x29, sp, #0x10
~ 0000de38: f90007e0 str x0, [sp, #8]
~ 0000de3c: b90007e1 str w1, [sp, #4]
~ 0000de40: b90003e2 str w2, [sp]
__vgic_v3_write_apxr1:879.24 (vgic-v3-sr.c) SbePe __vgic_v3_write_apxrn(║vcpu, rt, 1);
~ 0000de44: f94007e0 ldr x0, [sp, #8]
__vgic_v3_write_apxr1:879.30 (vgic-v3-sr.c) sbepe __vgic_v3_write_apxrn(vcpu, ║rt, 1);
~ 0000de48: b94003e1 ldr w1, [sp]
~ 0000de4c: 52800022 mov w2, #0x1 // #1
__vgic_v3_write_apxr1:879.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_apxrn(vcpu, rt, 1);
~ 0000de50: 94000463 bl efdc <__vgic_v3_write_apxrn>
__vgic_v3_write_apxr1:880.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000de54: a9417bfd ldp x29, x30, [sp, #16] <- 0000de50(bl-succ)<return>
~ 0000de58: 910083ff add sp, sp, #0x20
0000de38 CFA:r29+16 r29:c-16 r30:c-8
~ 0000de5c: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xde2c 0xde60 (DW_OP_breg31 0x8) __vgic_v3_write_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:877
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xde2c 0xde60 (DW_OP_breg31 0x4) __vgic_v3_write_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:877
-rt param int (base type, DW_ATE_signed size:4) 0xde2c 0xde60 (DW_OP_breg31 0x0) __vgic_v3_write_apxr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:877
**0000de60 <__vgic_v3_read_apxr2>:
+ __vgic_v3_read_apxr2 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xde60 0xde94 (DW_OP_breg31 0x8)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xde60 0xde94 (DW_OP_breg31 0x4)
+rt param int (base type, DW_ATE_signed size:4) 0xde60 0xde94 (DW_OP_breg31 0x0)
__vgic_v3_read_apxr2:863.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xde60 0xde94 (DW_OP_breg31 0x8) __vgic_v3_read_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:862
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xde60 0xde94 (DW_OP_breg31 0x4) __vgic_v3_read_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:862
+rt param int (base type, DW_ATE_signed size:4) 0xde60 0xde94 (DW_OP_breg31 0x0) __vgic_v3_read_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:862
~ 0000de60: d10083ff sub sp, sp, #0x20
~ 0000de64: a9017bfd stp x29, x30, [sp, #16]
0000de60 CFA:r31 r29:u r30:u
~ 0000de68: 910043fd add x29, sp, #0x10
~ 0000de6c: f90007e0 str x0, [sp, #8]
~ 0000de70: b90007e1 str w1, [sp, #4]
~ 0000de74: b90003e2 str w2, [sp]
__vgic_v3_read_apxr2:864.23 (vgic-v3-sr.c) SbePe __vgic_v3_read_apxrn(║vcpu, rt, 2);
~ 0000de78: f94007e0 ldr x0, [sp, #8]
__vgic_v3_read_apxr2:864.29 (vgic-v3-sr.c) sbepe __vgic_v3_read_apxrn(vcpu, ║rt, 2);
~ 0000de7c: b94003e1 ldr w1, [sp]
~ 0000de80: 52800042 mov w2, #0x2 // #2
__vgic_v3_read_apxr2:864.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_read_apxrn(vcpu, rt, 2);
~ 0000de84: 9400042f bl ef40 <__vgic_v3_read_apxrn>
__vgic_v3_read_apxr2:865.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000de88: a9417bfd ldp x29, x30, [sp, #16] <- 0000de84(bl-succ)<return>
~ 0000de8c: 910083ff add sp, sp, #0x20
0000de6c CFA:r29+16 r29:c-16 r30:c-8
~ 0000de90: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xde60 0xde94 (DW_OP_breg31 0x8) __vgic_v3_read_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:862
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xde60 0xde94 (DW_OP_breg31 0x4) __vgic_v3_read_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:862
-rt param int (base type, DW_ATE_signed size:4) 0xde60 0xde94 (DW_OP_breg31 0x0) __vgic_v3_read_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:862
**0000de94 <__vgic_v3_write_apxr2>:
+ __vgic_v3_write_apxr2 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xde94 0xdec8 (DW_OP_breg31 0x8)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xde94 0xdec8 (DW_OP_breg31 0x4)
+rt param int (base type, DW_ATE_signed size:4) 0xde94 0xdec8 (DW_OP_breg31 0x0)
__vgic_v3_write_apxr2:883.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xde94 0xdec8 (DW_OP_breg31 0x8) __vgic_v3_write_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:882
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xde94 0xdec8 (DW_OP_breg31 0x4) __vgic_v3_write_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:882
+rt param int (base type, DW_ATE_signed size:4) 0xde94 0xdec8 (DW_OP_breg31 0x0) __vgic_v3_write_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:882
~ 0000de94: d10083ff sub sp, sp, #0x20
~ 0000de98: a9017bfd stp x29, x30, [sp, #16]
0000de94 CFA:r31 r29:u r30:u
~ 0000de9c: 910043fd add x29, sp, #0x10
~ 0000dea0: f90007e0 str x0, [sp, #8]
~ 0000dea4: b90007e1 str w1, [sp, #4]
~ 0000dea8: b90003e2 str w2, [sp]
__vgic_v3_write_apxr2:884.24 (vgic-v3-sr.c) SbePe __vgic_v3_write_apxrn(║vcpu, rt, 2);
~ 0000deac: f94007e0 ldr x0, [sp, #8]
__vgic_v3_write_apxr2:884.30 (vgic-v3-sr.c) sbepe __vgic_v3_write_apxrn(vcpu, ║rt, 2);
~ 0000deb0: b94003e1 ldr w1, [sp]
~ 0000deb4: 52800042 mov w2, #0x2 // #2
__vgic_v3_write_apxr2:884.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_apxrn(vcpu, rt, 2);
~ 0000deb8: 94000449 bl efdc <__vgic_v3_write_apxrn>
__vgic_v3_write_apxr2:885.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000debc: a9417bfd ldp x29, x30, [sp, #16] <- 0000deb8(bl-succ)<return>
~ 0000dec0: 910083ff add sp, sp, #0x20
0000dea0 CFA:r29+16 r29:c-16 r30:c-8
~ 0000dec4: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xde94 0xdec8 (DW_OP_breg31 0x8) __vgic_v3_write_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:882
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xde94 0xdec8 (DW_OP_breg31 0x4) __vgic_v3_write_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:882
-rt param int (base type, DW_ATE_signed size:4) 0xde94 0xdec8 (DW_OP_breg31 0x0) __vgic_v3_write_apxr2:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:882
**0000dec8 <__vgic_v3_read_apxr3>:
+ __vgic_v3_read_apxr3 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdec8 0xdefc (DW_OP_breg31 0x8)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdec8 0xdefc (DW_OP_breg31 0x4)
+rt param int (base type, DW_ATE_signed size:4) 0xdec8 0xdefc (DW_OP_breg31 0x0)
__vgic_v3_read_apxr3:868.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdec8 0xdefc (DW_OP_breg31 0x8) __vgic_v3_read_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:867
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdec8 0xdefc (DW_OP_breg31 0x4) __vgic_v3_read_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:867
+rt param int (base type, DW_ATE_signed size:4) 0xdec8 0xdefc (DW_OP_breg31 0x0) __vgic_v3_read_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:867
~ 0000dec8: d10083ff sub sp, sp, #0x20
~ 0000decc: a9017bfd stp x29, x30, [sp, #16]
0000dec8 CFA:r31 r29:u r30:u
~ 0000ded0: 910043fd add x29, sp, #0x10
~ 0000ded4: f90007e0 str x0, [sp, #8]
~ 0000ded8: b90007e1 str w1, [sp, #4]
~ 0000dedc: b90003e2 str w2, [sp]
__vgic_v3_read_apxr3:869.23 (vgic-v3-sr.c) SbePe __vgic_v3_read_apxrn(║vcpu, rt, 3);
~ 0000dee0: f94007e0 ldr x0, [sp, #8]
__vgic_v3_read_apxr3:869.29 (vgic-v3-sr.c) sbepe __vgic_v3_read_apxrn(vcpu, ║rt, 3);
~ 0000dee4: b94003e1 ldr w1, [sp]
~ 0000dee8: 52800062 mov w2, #0x3 // #3
__vgic_v3_read_apxr3:869.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_read_apxrn(vcpu, rt, 3);
~ 0000deec: 94000415 bl ef40 <__vgic_v3_read_apxrn>
__vgic_v3_read_apxr3:870.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000def0: a9417bfd ldp x29, x30, [sp, #16] <- 0000deec(bl-succ)<return>
~ 0000def4: 910083ff add sp, sp, #0x20
0000ded4 CFA:r29+16 r29:c-16 r30:c-8
~ 0000def8: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdec8 0xdefc (DW_OP_breg31 0x8) __vgic_v3_read_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:867
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdec8 0xdefc (DW_OP_breg31 0x4) __vgic_v3_read_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:867
-rt param int (base type, DW_ATE_signed size:4) 0xdec8 0xdefc (DW_OP_breg31 0x0) __vgic_v3_read_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:867
**0000defc <__vgic_v3_write_apxr3>:
+ __vgic_v3_write_apxr3 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdefc 0xdf30 (DW_OP_breg31 0x8)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdefc 0xdf30 (DW_OP_breg31 0x4)
+rt param int (base type, DW_ATE_signed size:4) 0xdefc 0xdf30 (DW_OP_breg31 0x0)
__vgic_v3_write_apxr3:888.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdefc 0xdf30 (DW_OP_breg31 0x8) __vgic_v3_write_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:887
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdefc 0xdf30 (DW_OP_breg31 0x4) __vgic_v3_write_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:887
+rt param int (base type, DW_ATE_signed size:4) 0xdefc 0xdf30 (DW_OP_breg31 0x0) __vgic_v3_write_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:887
~ 0000defc: d10083ff sub sp, sp, #0x20
~ 0000df00: a9017bfd stp x29, x30, [sp, #16]
0000defc CFA:r31 r29:u r30:u
~ 0000df04: 910043fd add x29, sp, #0x10
~ 0000df08: f90007e0 str x0, [sp, #8]
~ 0000df0c: b90007e1 str w1, [sp, #4]
~ 0000df10: b90003e2 str w2, [sp]
__vgic_v3_write_apxr3:889.24 (vgic-v3-sr.c) SbePe __vgic_v3_write_apxrn(║vcpu, rt, 3);
~ 0000df14: f94007e0 ldr x0, [sp, #8]
__vgic_v3_write_apxr3:889.30 (vgic-v3-sr.c) sbepe __vgic_v3_write_apxrn(vcpu, ║rt, 3);
~ 0000df18: b94003e1 ldr w1, [sp]
~ 0000df1c: 52800062 mov w2, #0x3 // #3
__vgic_v3_write_apxr3:889.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_apxrn(vcpu, rt, 3);
~ 0000df20: 9400042f bl efdc <__vgic_v3_write_apxrn>
__vgic_v3_write_apxr3:890.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000df24: a9417bfd ldp x29, x30, [sp, #16] <- 0000df20(bl-succ)<return>
~ 0000df28: 910083ff add sp, sp, #0x20
0000df08 CFA:r29+16 r29:c-16 r30:c-8
~ 0000df2c: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdefc 0xdf30 (DW_OP_breg31 0x8) __vgic_v3_write_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:887
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdefc 0xdf30 (DW_OP_breg31 0x4) __vgic_v3_write_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:887
-rt param int (base type, DW_ATE_signed size:4) 0xdefc 0xdf30 (DW_OP_breg31 0x0) __vgic_v3_write_apxr3:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:887
**0000df30 <__vgic_v3_read_hppir>:
+ __vgic_v3_read_hppir params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdf30 0xe004 (DW_OP_breg31 0x20)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdf30 0xe004 (DW_OP_breg31 0x1c)
+rt param int (base type, DW_ATE_signed size:4) 0xdf30 0xe004 (DW_OP_breg31 0x18)
__vgic_v3_read_hppir:893.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdf30 0xe004 (DW_OP_breg31 0x20) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:892
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdf30 0xe004 (DW_OP_breg31 0x1c) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:892
+rt param int (base type, DW_ATE_signed size:4) 0xdf30 0xe004 (DW_OP_breg31 0x18) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:892
+lr_val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xdf30 0xe004 (DW_OP_breg31 0x10) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:894
+lr var int (base type, DW_ATE_signed size:4) 0xdf30 0xe004 (DW_OP_breg31 0xc) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:895
+lr_grp var int (base type, DW_ATE_signed size:4) 0xdf30 0xe004 (DW_OP_breg31 0x8) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:895
+grp var int (base type, DW_ATE_signed size:4) 0xdf30 0xe004 (DW_OP_breg31 0x4) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:895
~ 0000df30: d10143ff sub sp, sp, #0x50
~ 0000df34: a9047bfd stp x29, x30, [sp, #64]
0000df30 CFA:r31 r29:u r30:u
~ 0000df38: 910103fd add x29, sp, #0x40
~ 0000df3c: f90013e0 str x0, [sp, #32]
~ 0000df40: b9001fe1 str w1, [sp, #28]
~ 0000df44: b9001be2 str w2, [sp, #24]
__vgic_v3_read_hppir:897.28 (vgic-v3-sr.c) SbePe grp = __vgic_v3_get_group(║vcpu);
~ 0000df48: f94013e0 ldr x0, [sp, #32]
__vgic_v3_read_hppir:897.8 (vgic-v3-sr.c) sbepe grp = ║__vgic_v3_get_group(vcpu);
~ 0000df4c: 94000203 bl e758 <__vgic_v3_get_group>
__vgic_v3_read_hppir:897.6 (vgic-v3-sr.c) sbepe grp ║= __vgic_v3_get_group(vcpu);
~ 0000df50: b90007e0 str w0, [sp, #4] <- 0000df4c(bl-succ)<return>
__vgic_v3_read_hppir:899.37 (vgic-v3-sr.c) Sbepe lr = __vgic_v3_highest_priority_lr(║vcpu, vmcr, &lr_val);
~ 0000df54: f94013e0 ldr x0, [sp, #32]
__vgic_v3_read_hppir:899.43 (vgic-v3-sr.c) sbepe lr = __vgic_v3_highest_priority_lr(vcpu, ║vmcr, &lr_val);
~ 0000df58: b9401fe1 ldr w1, [sp, #28]
~ 0000df5c: 910043e2 add x2, sp, #0x10
__vgic_v3_read_hppir:899.7 (vgic-v3-sr.c) sbepe lr = ║__vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
~ 0000df60: 9400020e bl e798 <__vgic_v3_highest_priority_lr>
__vgic_v3_read_hppir:899.5 (vgic-v3-sr.c) sbepe lr ║= __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
~ 0000df64: b9000fe0 str w0, [sp, #12] <- 0000df60(bl-succ)<return>
__vgic_v3_read_hppir:900.6 (vgic-v3-sr.c) Sbepe if (║lr == -1)
~ 0000df68: b9400fe8 ldr w8, [sp, #12]
__vgic_v3_read_hppir:900.6 (vgic-v3-sr.c) sbepe if (║lr == -1)
~ 0000df6c: 31000508 adds w8, w8, #0x1
~ ┌──0000df70: 54000061 b.ne df7c <__vgic_v3_read_hppir+0x4c> // b.any
│
~ │┌─0000df74: 14000001 b df78 <__vgic_v3_read_hppir+0x48> <- 0000df70(b.cc-succ)<fallthrough>
││
││ __vgic_v3_read_hppir:901.3 (vgic-v3-sr.c) Sbepe ║goto spurious;
~ ┌───┼└>0000df78: 1400000e b dfb0 <__vgic_v3_read_hppir+0x80> <- 0000df74(b)<__vgic_v3_read_hppir+0x48>
│ │
│ │ __vgic_v3_read_hppir:903.14 (vgic-v3-sr.c) Sbepe lr_grp = !!(║lr_val & ICH_LR_GROUP);
~ │ └─>0000df7c: f9400be8 ldr x8, [sp, #16] <- 0000df70(b.cc)<__vgic_v3_read_hppir+0x4c>
│ __vgic_v3_read_hppir:903.12 (vgic-v3-sr.c) sbepe lr_grp = !║!(lr_val & ICH_LR_GROUP);
~ │ 0000df80: d37cf108 ubfx x8, x8, #60, #1
│ __vgic_v3_read_hppir:903.9 (vgic-v3-sr.c) sbepe lr_grp ║= !!(lr_val & ICH_LR_GROUP);
~ │ 0000df84: b9000be8 str w8, [sp, #8]
│ __vgic_v3_read_hppir:904.6 (vgic-v3-sr.c) Sbepe if (║lr_grp != grp)
~ │ 0000df88: b9400be8 ldr w8, [sp, #8]
│ __vgic_v3_read_hppir:904.16 (vgic-v3-sr.c) sbepe if (lr_grp != ║grp)
~ │ 0000df8c: b94007e9 ldr w9, [sp, #4]
│ __vgic_v3_read_hppir:904.6 (vgic-v3-sr.c) sbepe if (║lr_grp != grp)
~ │ 0000df90: 6b090108 subs w8, w8, w9
~ │┌─────0000df94: 540000c0 b.eq dfac <__vgic_v3_read_hppir+0x7c> // b.none
││
~ ││ ┌─0000df98: 14000001 b df9c <__vgic_v3_read_hppir+0x6c> <- 0000df94(b.cc-succ)<fallthrough>
││ │
~ ││ └>0000df9c: 52807fe8 mov w8, #0x3ff // #1023 <- 0000df98(b)<__vgic_v3_read_hppir+0x6c>
~ ││ 0000dfa0: 2a0803e9 mov w9, w8
││ __vgic_v3_read_hppir:905.10 (vgic-v3-sr.c) Sbepe lr_val ║= ICC_IAR1_EL1_SPURIOUS;
~ ││ 0000dfa4: f9000be9 str x9, [sp, #16]
││ __vgic_v3_read_hppir:905.3 (vgic-v3-sr.c) sbepe ║lr_val = ICC_IAR1_EL1_SPURIOUS;
~ ││ ┌─0000dfa8: 14000001 b dfac <__vgic_v3_read_hppir+0x7c>
││ │
││ │ __vgic_v3_read_hppir:904.16 (vgic-v3-sr.c) Sbepe if (lr_grp != ║grp)
~ │└>┌─└>0000dfac: 14000001 b dfb0 <__vgic_v3_read_hppir+0x80> <- 0000df94(b.cc)<__vgic_v3_read_hppir+0x7c>,0000dfa8(b)<__vgic_v3_read_hppir+0x7c>
│ │
│ │ __vgic_v3_read_hppir:908.15 (vgic-v3-sr.c) Sbepe vcpu_set_reg(║vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
~ └─>└──>0000dfb0: f94013e8 ldr x8, [sp, #32] <- 0000df78(b)<__vgic_v3_read_hppir+0x80>,0000dfac(b)<__vgic_v3_read_hppir+0x80>
__vgic_v3_read_hppir:908.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
~ 0000dfb4: b9401be9 ldr w9, [sp, #24]
__vgic_v3_read_hppir:908.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║lr_val & ICH_LR_VIRTUAL_ID_MASK);
~ 0000dfb8: b94013ea ldr w10, [sp, #16]
~ 0000dfbc: 2a0a03eb mov w11, w10
~ 0000dfc0: f81f83a8 stur x8, [x29, #-8]
~ 0000dfc4: 381f43a9 sturb w9, [x29, #-12]
~ 0000dfc8: f81e83ab stur x11, [x29, #-24]
w: 0xdfcc 0xdff8 vcpu_set_reg inlined from __vgic_v3_read_hppir:908 (vgic-v3-sr.c) <a8e74>:
w vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdfcc 0xdff8 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdfcc 0xdff8 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xdfcc 0xdff8 (DW_OP_fbreg -0x18) vcpu_set_reg(inlined):__vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~w 0000dfcc: 385f43a9 ldurb w9, [x29, #-12]
w vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~w 0000dfd0: 71007d29 subs w9, w9, #0x1f
~w ┌───0000dfd4: 54000120 b.eq dff8 <__vgic_v3_read_hppir+0xc8> // b.none
│
~w │ ┌─0000dfd8: 14000001 b dfdc <__vgic_v3_read_hppir+0xac> <- 0000dfd4(b.cc-succ)<fallthrough>
│ │
w │ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~w │ └>0000dfdc: f85e83a8 ldur x8, [x29, #-24] <- 0000dfd8(b)<__vgic_v3_read_hppir+0xac>
w │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~w │ 0000dfe0: f85f83a9 ldur x9, [x29, #-8]
w │ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~w │ 0000dfe4: 385f43aa ldurb w10, [x29, #-12]
~w │ 0000dfe8: 2a0a03eb mov w11, w10
w │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~w │ 0000dfec: 8b0b0d29 add x9, x9, x11, lsl #3
w │ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~w │ 0000dff0: f900b128 str x8, [x9, #352]
w │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~w │ ┌─0000dff4: 14000001 b dff8 <__vgic_v3_read_hppir+0xc8>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdfcc 0xdff8 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xdfcc 0xdff8 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xdfcc 0xdff8 (DW_OP_fbreg -0x18) vcpu_set_reg(inlined):__vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
│ │ __vgic_v3_read_hppir:909.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000dff8: a9447bfd ldp x29, x30, [sp, #64] <- 0000dfd4(b.cc)<__vgic_v3_read_hppir+0xc8>,0000dff4(b)<__vgic_v3_read_hppir+0xc8>
~ 0000dffc: 910143ff add sp, sp, #0x50
0000df3c CFA:r29+16 r29:c-16 r30:c-8
~ 0000e000: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xdf30 0xe004 (DW_OP_breg31 0x20) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:892
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xdf30 0xe004 (DW_OP_breg31 0x1c) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:892
-rt param int (base type, DW_ATE_signed size:4) 0xdf30 0xe004 (DW_OP_breg31 0x18) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:892
-lr_val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xdf30 0xe004 (DW_OP_breg31 0x10) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:894
-lr var int (base type, DW_ATE_signed size:4) 0xdf30 0xe004 (DW_OP_breg31 0xc) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:895
-lr_grp var int (base type, DW_ATE_signed size:4) 0xdf30 0xe004 (DW_OP_breg31 0x8) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:895
-grp var int (base type, DW_ATE_signed size:4) 0xdf30 0xe004 (DW_OP_breg31 0x4) __vgic_v3_read_hppir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:895
**0000e004 <__vgic_v3_read_igrpen0>:
+ __vgic_v3_read_igrpen0 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe004 0xe068 (DW_OP_fbreg 0x10)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe004 0xe068 (DW_OP_fbreg 0xc)
+rt param int (base type, DW_ATE_signed size:4) 0xe004 0xe068 (DW_OP_fbreg 0x8)
__vgic_v3_read_igrpen0:748.0 (vgic-v3-sr.c) Sbepe ║{
0000e004 CFA:r31
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe004 0xe068 (DW_OP_fbreg 0x10) __vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:747
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe004 0xe068 (DW_OP_fbreg 0xc) __vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:747
+rt param int (base type, DW_ATE_signed size:4) 0xe004 0xe068 (DW_OP_fbreg 0x8) __vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:747
~ 0000e004: d100c3ff sub sp, sp, #0x30
~ 0000e008: f9000be0 str x0, [sp, #16]
~ 0000e00c: b9000fe1 str w1, [sp, #12]
~ 0000e010: b9000be2 str w2, [sp, #8]
__vgic_v3_read_igrpen0:749.15 (vgic-v3-sr.c) SbePe vcpu_set_reg(║vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK));
~ 0000e014: f9400be8 ldr x8, [sp, #16]
__vgic_v3_read_igrpen0:749.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, !!(vmcr & ICH_VMCR_ENG0_MASK));
~ 0000e018: b9400be9 ldr w9, [sp, #8]
__vgic_v3_read_igrpen0:749.28 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, !!(║vmcr & ICH_VMCR_ENG0_MASK));
~ 0000e01c: b9400fea ldr w10, [sp, #12]
~ 0000e020: 2a0a03eb mov w11, w10
__vgic_v3_read_igrpen0:749.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║!!(vmcr & ICH_VMCR_ENG0_MASK));
~ 0000e024: 9240016b and x11, x11, #0x1
~ 0000e028: f90017e8 str x8, [sp, #40]
~ 0000e02c: 390093e9 strb w9, [sp, #36]
~ 0000e030: f9000feb str x11, [sp, #24]
x: 0xe034 0xe060 vcpu_set_reg inlined from __vgic_v3_read_igrpen0:749 (vgic-v3-sr.c) <a8ee6>:
x vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe034 0xe060 (DW_OP_fbreg 0x28) vcpu_set_reg(inlined):__vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe034 0xe060 (DW_OP_fbreg 0x24) vcpu_set_reg(inlined):__vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe034 0xe060 (DW_OP_fbreg 0x18) vcpu_set_reg(inlined):__vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~x 0000e034: 394093e9 ldrb w9, [sp, #36]
x vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~x 0000e038: 71007d29 subs w9, w9, #0x1f
~x ┌───0000e03c: 54000120 b.eq e060 <__vgic_v3_read_igrpen0+0x5c> // b.none
│
~x │ ┌─0000e040: 14000001 b e044 <__vgic_v3_read_igrpen0+0x40> <- 0000e03c(b.cc-succ)<fallthrough>
│ │
x │ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~x │ └>0000e044: f9400fe8 ldr x8, [sp, #24] <- 0000e040(b)<__vgic_v3_read_igrpen0+0x40>
x │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~x │ 0000e048: f94017e9 ldr x9, [sp, #40]
x │ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~x │ 0000e04c: 394093ea ldrb w10, [sp, #36]
~x │ 0000e050: 2a0a03eb mov w11, w10
x │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~x │ 0000e054: 8b0b0d29 add x9, x9, x11, lsl #3
x │ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~x │ 0000e058: f900b128 str x8, [x9, #352]
x │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~x │ ┌─0000e05c: 14000001 b e060 <__vgic_v3_read_igrpen0+0x5c>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe034 0xe060 (DW_OP_fbreg 0x28) vcpu_set_reg(inlined):__vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe034 0xe060 (DW_OP_fbreg 0x24) vcpu_set_reg(inlined):__vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe034 0xe060 (DW_OP_fbreg 0x18) vcpu_set_reg(inlined):__vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
│ │ __vgic_v3_read_igrpen0:750.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000e060: 9100c3ff add sp, sp, #0x30 <- 0000e03c(b.cc)<__vgic_v3_read_igrpen0+0x5c>,0000e05c(b)<__vgic_v3_read_igrpen0+0x5c>
0000e008 CFA:r31+48
~ 0000e064: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe004 0xe068 (DW_OP_fbreg 0x10) __vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:747
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe004 0xe068 (DW_OP_fbreg 0xc) __vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:747
-rt param int (base type, DW_ATE_signed size:4) 0xe004 0xe068 (DW_OP_fbreg 0x8) __vgic_v3_read_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:747
**0000e068 <__vgic_v3_write_igrpen0>:
+ __vgic_v3_write_igrpen0 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe068 0xe110 (DW_OP_breg31 0x18)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe068 0xe110 (DW_OP_breg31 0x14)
+rt param int (base type, DW_ATE_signed size:4) 0xe068 0xe110 (DW_OP_breg31 0x10)
__vgic_v3_write_igrpen0:758.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe068 0xe110 (DW_OP_breg31 0x18) __vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:757
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe068 0xe110 (DW_OP_breg31 0x14) __vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:757
+rt param int (base type, DW_ATE_signed size:4) 0xe068 0xe110 (DW_OP_breg31 0x10) __vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:757
+val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe068 0xe110 (DW_OP_breg31 0x8) __vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:759
~ 0000e068: d10103ff sub sp, sp, #0x40
~ 0000e06c: a9037bfd stp x29, x30, [sp, #48]
0000e068 CFA:r31 r29:u r30:u
~ 0000e070: 9100c3fd add x29, sp, #0x30
~ 0000e074: f9000fe0 str x0, [sp, #24]
~ 0000e078: b90017e1 str w1, [sp, #20]
~ 0000e07c: b90013e2 str w2, [sp, #16]
__vgic_v3_write_igrpen0:759.25 (vgic-v3-sr.c) SbePe u64 val = vcpu_get_reg(║vcpu, rt);
~ 0000e080: f9400fe8 ldr x8, [sp, #24]
__vgic_v3_write_igrpen0:759.31 (vgic-v3-sr.c) sbepe u64 val = vcpu_get_reg(vcpu, ║rt);
~ 0000e084: b94013e9 ldr w9, [sp, #16]
~ 0000e088: f81f83a8 stur x8, [x29, #-8]
~ 0000e08c: 381f43a9 sturb w9, [x29, #-12]
y: 0xe090 0xe0c8 vcpu_get_reg inlined from __vgic_v3_write_igrpen0:759 (vgic-v3-sr.c) <a8f67>:
y vcpu_get_reg:166.10 (kvm_emulate.h) Sbepe return (║reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe090 0xe0c8 (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe090 0xe0c8 (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~y 0000e090: 385f43a9 ldurb w9, [x29, #-12]
y vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~y 0000e094: 71007d29 subs w9, w9, #0x1f
~y ┌──0000e098: 540000a1 b.ne e0ac <__vgic_v3_write_igrpen0+0x44> // b.any
│
~y │┌─0000e09c: 14000001 b e0a0 <__vgic_v3_write_igrpen0+0x38> <- 0000e098(b.cc-succ)<fallthrough>
││
~y │└>0000e0a0: aa1f03e0 mov x0, xzr <- 0000e09c(b)<__vgic_v3_write_igrpen0+0x38>
~y │ 0000e0a4: f90003e0 str x0, [sp]
y │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~y ┌┼──0000e0a8: 14000008 b e0c8 <__vgic_v3_write_igrpen0+0x60>
││
y ││ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~y │└─>0000e0ac: f85f83a8 ldur x8, [x29, #-8] <- 0000e098(b.cc)<__vgic_v3_write_igrpen0+0x44>
y │ vcpu_get_reg:166.56 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[║reg_num];
~y │ 0000e0b0: 385f43a9 ldurb w9, [x29, #-12]
~y │ 0000e0b4: 2a0903ea mov w10, w9
y │ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~y │ 0000e0b8: 8b0a0d08 add x8, x8, x10, lsl #3
~y │ 0000e0bc: f940b108 ldr x8, [x8, #352]
~y │ 0000e0c0: f90003e8 str x8, [sp]
y │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~y │ ┌─0000e0c4: 14000001 b e0c8 <__vgic_v3_write_igrpen0+0x60>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe090 0xe0c8 (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe090 0xe0c8 (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
~ └>└>0000e0c8: f94003e8 ldr x8, [sp] <- 0000e0a8(b)<__vgic_v3_write_igrpen0+0x60>,0000e0c4(b)<__vgic_v3_write_igrpen0+0x60>
__vgic_v3_write_igrpen0:759.6 (vgic-v3-sr.c) Sbepe u64 ║val = vcpu_get_reg(vcpu, rt);
~ 0000e0cc: f90007e8 str x8, [sp, #8]
__vgic_v3_write_igrpen0:761.6 (vgic-v3-sr.c) Sbepe if (║val & 1)
~ 0000e0d0: 394023e9 ldrb w9, [sp, #8]
~ ┌──0000e0d4: 360000c9 tbz w9, #0, e0ec <__vgic_v3_write_igrpen0+0x84>
│
~ │┌─0000e0d8: 14000001 b e0dc <__vgic_v3_write_igrpen0+0x74> <- 0000e0d4(b.cc-succ)<fallthrough>
││
││ __vgic_v3_write_igrpen0:762.8 (vgic-v3-sr.c) Sbepe vmcr ║|= ICH_VMCR_ENG0_MASK;
~ │└>0000e0dc: b94017e8 ldr w8, [sp, #20] <- 0000e0d8(b)<__vgic_v3_write_igrpen0+0x74>
~ │ 0000e0e0: 32000108 orr w8, w8, #0x1
~ │ 0000e0e4: b90017e8 str w8, [sp, #20]
│ __vgic_v3_write_igrpen0:762.3 (vgic-v3-sr.c) sbepe ║vmcr |= ICH_VMCR_ENG0_MASK;
~ ┌┼──0000e0e8: 14000005 b e0fc <__vgic_v3_write_igrpen0+0x94>
││
││ __vgic_v3_write_igrpen0:764.8 (vgic-v3-sr.c) Sbepe vmcr ║&= ~ICH_VMCR_ENG0_MASK;
~ │└─>0000e0ec: b94017e8 ldr w8, [sp, #20] <- 0000e0d4(b.cc)<__vgic_v3_write_igrpen0+0x84>
~ │ 0000e0f0: 121f7908 and w8, w8, #0xfffffffe
~ │ 0000e0f4: b90017e8 str w8, [sp, #20]
~ │ ┌─0000e0f8: 14000001 b e0fc <__vgic_v3_write_igrpen0+0x94>
│ │
│ │ __vgic_v3_write_igrpen0:766.23 (vgic-v3-sr.c) Sbepe __vgic_v3_write_vmcr(║vmcr);
~ └>└>0000e0fc: b94017e0 ldr w0, [sp, #20] <- 0000e0e8(b)<__vgic_v3_write_igrpen0+0x94>,0000e0f8(b)<__vgic_v3_write_igrpen0+0x94>
__vgic_v3_write_igrpen0:766.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_vmcr(vmcr);
~ 0000e100: 97fffbf9 bl d0e4 <__vgic_v3_write_vmcr>
__vgic_v3_write_igrpen0:767.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000e104: a9437bfd ldp x29, x30, [sp, #48] <- 0000e100(bl-succ)<return>
~ 0000e108: 910103ff add sp, sp, #0x40
0000e074 CFA:r29+16 r29:c-16 r30:c-8
~ 0000e10c: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe068 0xe110 (DW_OP_breg31 0x18) __vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:757
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe068 0xe110 (DW_OP_breg31 0x14) __vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:757
-rt param int (base type, DW_ATE_signed size:4) 0xe068 0xe110 (DW_OP_breg31 0x10) __vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:757
-val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe068 0xe110 (DW_OP_breg31 0x8) __vgic_v3_write_igrpen0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:759
**0000e110 <__vgic_v3_read_bpr0>:
+ __vgic_v3_read_bpr0 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe110 0xe194 (DW_OP_breg31 0x20)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe110 0xe194 (DW_OP_breg31 0x1c)
+rt param int (base type, DW_ATE_signed size:4) 0xe110 0xe194 (DW_OP_breg31 0x18)
__vgic_v3_read_bpr0:782.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe110 0xe194 (DW_OP_breg31 0x20) __vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:781
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe110 0xe194 (DW_OP_breg31 0x1c) __vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:781
+rt param int (base type, DW_ATE_signed size:4) 0xe110 0xe194 (DW_OP_breg31 0x18) __vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:781
~ 0000e110: d10143ff sub sp, sp, #0x50
~ 0000e114: a9047bfd stp x29, x30, [sp, #64]
0000e110 CFA:r31 r29:u r30:u
~ 0000e118: 910103fd add x29, sp, #0x40
~ 0000e11c: f90013e0 str x0, [sp, #32]
~ 0000e120: b9001fe1 str w1, [sp, #28]
~ 0000e124: b9001be2 str w2, [sp, #24]
__vgic_v3_read_bpr0:783.15 (vgic-v3-sr.c) SbePe vcpu_set_reg(║vcpu, rt, __vgic_v3_get_bpr0(vmcr));
~ 0000e128: f94013e8 ldr x8, [sp, #32]
__vgic_v3_read_bpr0:783.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, __vgic_v3_get_bpr0(vmcr));
~ 0000e12c: b9401be9 ldr w9, [sp, #24]
__vgic_v3_read_bpr0:783.44 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr0(║vmcr));
~ 0000e130: b9401fe0 ldr w0, [sp, #28]
~ 0000e134: f9000be8 str x8, [sp, #16]
~ 0000e138: b9000fe9 str w9, [sp, #12]
__vgic_v3_read_bpr0:783.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║__vgic_v3_get_bpr0(vmcr));
~ 0000e13c: 9400027b bl eb28 <__vgic_v3_get_bpr0>
~ 0000e140: 2a0003e9 mov w9, w0 <- 0000e13c(bl-succ)<return>
~ 0000e144: 2a0903e8 mov w8, w9
~ 0000e148: f9400bea ldr x10, [sp, #16]
~ 0000e14c: f81f83aa stur x10, [x29, #-8]
~ 0000e150: b9400fe9 ldr w9, [sp, #12]
~ 0000e154: 381f43a9 sturb w9, [x29, #-12]
~ 0000e158: f81e83a8 stur x8, [x29, #-24]
z: 0xe15c 0xe188 vcpu_set_reg inlined from __vgic_v3_read_bpr0:783 (vgic-v3-sr.c) <a8fd1>:
z vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe15c 0xe188 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe15c 0xe188 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe15c 0xe188 (DW_OP_fbreg -0x18) vcpu_set_reg(inlined):__vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~z 0000e15c: 385f43a9 ldurb w9, [x29, #-12]
z vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~z 0000e160: 71007d29 subs w9, w9, #0x1f
~z ┌───0000e164: 54000120 b.eq e188 <__vgic_v3_read_bpr0+0x78> // b.none
│
~z │ ┌─0000e168: 14000001 b e16c <__vgic_v3_read_bpr0+0x5c> <- 0000e164(b.cc-succ)<fallthrough>
│ │
z │ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~z │ └>0000e16c: f85e83a8 ldur x8, [x29, #-24] <- 0000e168(b)<__vgic_v3_read_bpr0+0x5c>
z │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~z │ 0000e170: f85f83a9 ldur x9, [x29, #-8]
z │ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~z │ 0000e174: 385f43aa ldurb w10, [x29, #-12]
~z │ 0000e178: 2a0a03eb mov w11, w10
z │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~z │ 0000e17c: 8b0b0d29 add x9, x9, x11, lsl #3
z │ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~z │ 0000e180: f900b128 str x8, [x9, #352]
z │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~z │ ┌─0000e184: 14000001 b e188 <__vgic_v3_read_bpr0+0x78>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe15c 0xe188 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe15c 0xe188 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe15c 0xe188 (DW_OP_fbreg -0x18) vcpu_set_reg(inlined):__vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
│ │ __vgic_v3_read_bpr0:784.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000e188: a9447bfd ldp x29, x30, [sp, #64] <- 0000e164(b.cc)<__vgic_v3_read_bpr0+0x78>,0000e184(b)<__vgic_v3_read_bpr0+0x78>
~ 0000e18c: 910143ff add sp, sp, #0x50
0000e11c CFA:r29+16 r29:c-16 r30:c-8
~ 0000e190: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe110 0xe194 (DW_OP_breg31 0x20) __vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:781
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe110 0xe194 (DW_OP_breg31 0x1c) __vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:781
-rt param int (base type, DW_ATE_signed size:4) 0xe110 0xe194 (DW_OP_breg31 0x18) __vgic_v3_read_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:781
**0000e194 <__vgic_v3_write_bpr0>:
+ __vgic_v3_write_bpr0 params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe194 0xe27c (DW_OP_fbreg -0x18)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe194 0xe27c (DW_OP_fbreg -0x1c)
+rt param int (base type, DW_ATE_signed size:4) 0xe194 0xe27c (DW_OP_breg31 0x20)
__vgic_v3_write_bpr0:792.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe194 0xe27c (DW_OP_fbreg -0x18) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:791
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe194 0xe27c (DW_OP_fbreg -0x1c) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:791
+rt param int (base type, DW_ATE_signed size:4) 0xe194 0xe27c (DW_OP_breg31 0x20) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:791
+val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe194 0xe27c (DW_OP_breg31 0x18) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:793
+bpr_min var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe194 0xe27c (DW_OP_breg31 0x14) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:794
~ 0000e194: d10143ff sub sp, sp, #0x50
~ 0000e198: a9047bfd stp x29, x30, [sp, #64]
0000e194 CFA:r31 r29:u r30:u
~ 0000e19c: 910103fd add x29, sp, #0x40
~ 0000e1a0: f81e83a0 stur x0, [x29, #-24]
~ 0000e1a4: b81e43a1 stur w1, [x29, #-28]
~ 0000e1a8: b90023e2 str w2, [sp, #32]
__vgic_v3_write_bpr0:793.25 (vgic-v3-sr.c) SbePe u64 val = vcpu_get_reg(║vcpu, rt);
~ 0000e1ac: f85e83a8 ldur x8, [x29, #-24]
__vgic_v3_write_bpr0:793.31 (vgic-v3-sr.c) sbepe u64 val = vcpu_get_reg(vcpu, ║rt);
~ 0000e1b0: b94023e9 ldr w9, [sp, #32]
~ 0000e1b4: f81f83a8 stur x8, [x29, #-8]
~ 0000e1b8: 381f43a9 sturb w9, [x29, #-12]
a: 0xe1bc 0xe1f4 vcpu_get_reg inlined from __vgic_v3_write_bpr0:793 (vgic-v3-sr.c) <a9061>:
a vcpu_get_reg:166.10 (kvm_emulate.h) Sbepe return (║reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe1bc 0xe1f4 (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe1bc 0xe1f4 (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~a 0000e1bc: 385f43a9 ldurb w9, [x29, #-12]
a vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~a 0000e1c0: 71007d29 subs w9, w9, #0x1f
~a ┌──0000e1c4: 540000a1 b.ne e1d8 <__vgic_v3_write_bpr0+0x44> // b.any
│
~a │┌─0000e1c8: 14000001 b e1cc <__vgic_v3_write_bpr0+0x38> <- 0000e1c4(b.cc-succ)<fallthrough>
││
~a │└>0000e1cc: aa1f03e0 mov x0, xzr <- 0000e1c8(b)<__vgic_v3_write_bpr0+0x38>
~a │ 0000e1d0: f90007e0 str x0, [sp, #8]
a │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~a ┌┼──0000e1d4: 14000008 b e1f4 <__vgic_v3_write_bpr0+0x60>
││
a ││ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~a │└─>0000e1d8: f85f83a8 ldur x8, [x29, #-8] <- 0000e1c4(b.cc)<__vgic_v3_write_bpr0+0x44>
a │ vcpu_get_reg:166.56 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[║reg_num];
~a │ 0000e1dc: 385f43a9 ldurb w9, [x29, #-12]
~a │ 0000e1e0: 2a0903ea mov w10, w9
a │ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~a │ 0000e1e4: 8b0a0d08 add x8, x8, x10, lsl #3
~a │ 0000e1e8: f940b108 ldr x8, [x8, #352]
~a │ 0000e1ec: f90007e8 str x8, [sp, #8]
a │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~a │ ┌─0000e1f0: 14000001 b e1f4 <__vgic_v3_write_bpr0+0x60>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe1bc 0xe1f4 (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe1bc 0xe1f4 (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
~ └>└>0000e1f4: f94007e8 ldr x8, [sp, #8] <- 0000e1d4(b)<__vgic_v3_write_bpr0+0x60>,0000e1f0(b)<__vgic_v3_write_bpr0+0x60>
__vgic_v3_write_bpr0:793.6 (vgic-v3-sr.c) Sbepe u64 ║val = vcpu_get_reg(vcpu, rt);
~ 0000e1f8: f9000fe8 str x8, [sp, #24]
__vgic_v3_write_bpr0:794.15 (vgic-v3-sr.c) Sbepe u8 bpr_min = ║__vgic_v3_bpr_min() - 1;
~ 0000e1fc: 94000241 bl eb00 <__vgic_v3_bpr_min>
__vgic_v3_write_bpr0:794.35 (vgic-v3-sr.c) sbepe u8 bpr_min = __vgic_v3_bpr_min() ║- 1;
~ 0000e200: 71000409 subs w9, w0, #0x1 <- 0000e1fc(bl-succ)<return>
__vgic_v3_write_bpr0:794.5 (vgic-v3-sr.c) sbepe u8 ║bpr_min = __vgic_v3_bpr_min() - 1;
~ 0000e204: 390053e9 strb w9, [sp, #20]
__vgic_v3_write_bpr0:797.6 (vgic-v3-sr.c) Sbepe if (║val < bpr_min)
~ 0000e208: f9400fe8 ldr x8, [sp, #24]
__vgic_v3_write_bpr0:797.12 (vgic-v3-sr.c) sbepe if (val < ║bpr_min)
~ 0000e20c: 394053e9 ldrb w9, [sp, #20]
~ 0000e210: 2a0903ea mov w10, w9
__vgic_v3_write_bpr0:797.6 (vgic-v3-sr.c) sbepe if (║val < bpr_min)
~ 0000e214: eb0a0108 subs x8, x8, x10
~ ┌───0000e218: 540000c2 b.cs e230 <__vgic_v3_write_bpr0+0x9c> // b.hs, b.nlast
│
~ │ ┌─0000e21c: 14000001 b e220 <__vgic_v3_write_bpr0+0x8c> <- 0000e218(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_write_bpr0:798.9 (vgic-v3-sr.c) Sbepe val = ║bpr_min;
~ │ └>0000e220: 394053e8 ldrb w8, [sp, #20] <- 0000e21c(b)<__vgic_v3_write_bpr0+0x8c>
~ │ 0000e224: 2a0803e9 mov w9, w8
│ __vgic_v3_write_bpr0:798.7 (vgic-v3-sr.c) sbepe val ║= bpr_min;
~ │ 0000e228: f9000fe9 str x9, [sp, #24]
│ __vgic_v3_write_bpr0:798.3 (vgic-v3-sr.c) sbepe ║val = bpr_min;
~ │ ┌─0000e22c: 14000001 b e230 <__vgic_v3_write_bpr0+0x9c>
│ │
│ │ __vgic_v3_write_bpr0:800.6 (vgic-v3-sr.c) Sbepe val ║<<= ICH_VMCR_BPR0_SHIFT;
~ └>└>0000e230: f9400fe8 ldr x8, [sp, #24] <- 0000e218(b.cc)<__vgic_v3_write_bpr0+0x9c>,0000e22c(b)<__vgic_v3_write_bpr0+0x9c>
~ 0000e234: d36ba908 lsl x8, x8, #21
~ 0000e238: f9000fe8 str x8, [sp, #24]
__vgic_v3_write_bpr0:801.6 (vgic-v3-sr.c) Sbepe val ║&= ICH_VMCR_BPR0_MASK;
~ 0000e23c: f9400fe8 ldr x8, [sp, #24]
~ 0000e240: 926b0908 and x8, x8, #0xe00000
~ 0000e244: f9000fe8 str x8, [sp, #24]
__vgic_v3_write_bpr0:802.7 (vgic-v3-sr.c) Sbepe vmcr ║&= ~ICH_VMCR_BPR0_MASK;
~ 0000e248: b85e43a9 ldur w9, [x29, #-28]
~ 0000e24c: 12087129 and w9, w9, #0xff1fffff
~ 0000e250: b81e43a9 stur w9, [x29, #-28]
__vgic_v3_write_bpr0:803.10 (vgic-v3-sr.c) Sbepe vmcr |= ║val;
~ 0000e254: b9401be9 ldr w9, [sp, #24]
__vgic_v3_write_bpr0:803.7 (vgic-v3-sr.c) sbepe vmcr ║|= val;
~ 0000e258: b85e43aa ldur w10, [x29, #-28]
~ 0000e25c: 2a090149 orr w9, w10, w9
~ 0000e260: 2a0903e0 mov w0, w9
~ 0000e264: b81e43a0 stur w0, [x29, #-28]
__vgic_v3_write_bpr0:805.23 (vgic-v3-sr.c) Sbepe __vgic_v3_write_vmcr(║vmcr);
~ 0000e268: b85e43a0 ldur w0, [x29, #-28]
__vgic_v3_write_bpr0:805.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_vmcr(vmcr);
~ 0000e26c: 97fffb9e bl d0e4 <__vgic_v3_write_vmcr>
__vgic_v3_write_bpr0:806.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000e270: a9447bfd ldp x29, x30, [sp, #64] <- 0000e26c(bl-succ)<return>
~ 0000e274: 910143ff add sp, sp, #0x50
0000e1a0 CFA:r29+16 r29:c-16 r30:c-8
~ 0000e278: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe194 0xe27c (DW_OP_fbreg -0x18) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:791
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe194 0xe27c (DW_OP_fbreg -0x1c) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:791
-rt param int (base type, DW_ATE_signed size:4) 0xe194 0xe27c (DW_OP_breg31 0x20) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:791
-val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe194 0xe27c (DW_OP_breg31 0x18) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:793
-bpr_min var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe194 0xe27c (DW_OP_breg31 0x14) __vgic_v3_write_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:794
**0000e27c <__vgic_v3_write_dir>:
+ __vgic_v3_write_dir params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe27c 0xe350 (DW_OP_fbreg -0x18)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe27c 0xe350 (DW_OP_fbreg -0x1c)
+rt param int (base type, DW_ATE_signed size:4) 0xe27c 0xe350 (DW_OP_breg31 0x20)
__vgic_v3_write_dir:688.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe27c 0xe350 (DW_OP_fbreg -0x18) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:687
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe27c 0xe350 (DW_OP_fbreg -0x1c) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:687
+rt param int (base type, DW_ATE_signed size:4) 0xe27c 0xe350 (DW_OP_breg31 0x20) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:687
+vid var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe27c 0xe350 (DW_OP_breg31 0x1c) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:689
+lr_val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe27c 0xe350 (DW_OP_breg31 0x10) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:690
+lr var int (base type, DW_ATE_signed size:4) 0xe27c 0xe350 (DW_OP_breg31 0xc) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:691
~ 0000e27c: d10143ff sub sp, sp, #0x50
~ 0000e280: a9047bfd stp x29, x30, [sp, #64]
0000e27c CFA:r31 r29:u r30:u
~ 0000e284: 910103fd add x29, sp, #0x40
~ 0000e288: f81e83a0 stur x0, [x29, #-24]
~ 0000e28c: b81e43a1 stur w1, [x29, #-28]
~ 0000e290: b90023e2 str w2, [sp, #32]
__vgic_v3_write_dir:689.25 (vgic-v3-sr.c) SbePe u32 vid = vcpu_get_reg(║vcpu, rt);
~ 0000e294: f85e83a8 ldur x8, [x29, #-24]
__vgic_v3_write_dir:689.31 (vgic-v3-sr.c) sbepe u32 vid = vcpu_get_reg(vcpu, ║rt);
~ 0000e298: b94023e9 ldr w9, [sp, #32]
~ 0000e29c: f81f83a8 stur x8, [x29, #-8]
~ 0000e2a0: 381f43a9 sturb w9, [x29, #-12]
b: 0xe2a4 0xe2dc vcpu_get_reg inlined from __vgic_v3_write_dir:689 (vgic-v3-sr.c) <a90f8>:
b vcpu_get_reg:166.10 (kvm_emulate.h) Sbepe return (║reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe2a4 0xe2dc (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe2a4 0xe2dc (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~b 0000e2a4: 385f43a9 ldurb w9, [x29, #-12]
b vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~b 0000e2a8: 71007d29 subs w9, w9, #0x1f
~b ┌──0000e2ac: 540000a1 b.ne e2c0 <__vgic_v3_write_dir+0x44> // b.any
│
~b │┌─0000e2b0: 14000001 b e2b4 <__vgic_v3_write_dir+0x38> <- 0000e2ac(b.cc-succ)<fallthrough>
││
~b │└>0000e2b4: aa1f03e0 mov x0, xzr <- 0000e2b0(b)<__vgic_v3_write_dir+0x38>
~b │ 0000e2b8: f90003e0 str x0, [sp]
b │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~b ┌┼──0000e2bc: 14000008 b e2dc <__vgic_v3_write_dir+0x60>
││
b ││ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~b │└─>0000e2c0: f85f83a8 ldur x8, [x29, #-8] <- 0000e2ac(b.cc)<__vgic_v3_write_dir+0x44>
b │ vcpu_get_reg:166.56 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[║reg_num];
~b │ 0000e2c4: 385f43a9 ldurb w9, [x29, #-12]
~b │ 0000e2c8: 2a0903ea mov w10, w9
b │ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~b │ 0000e2cc: 8b0a0d08 add x8, x8, x10, lsl #3
~b │ 0000e2d0: f940b108 ldr x8, [x8, #352]
~b │ 0000e2d4: f90003e8 str x8, [sp]
b │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~b │ ┌─0000e2d8: 14000001 b e2dc <__vgic_v3_write_dir+0x60>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe2a4 0xe2dc (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe2a4 0xe2dc (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
~ └>└>0000e2dc: f94003e0 ldr x0, [sp] <- 0000e2bc(b)<__vgic_v3_write_dir+0x60>,0000e2d8(b)<__vgic_v3_write_dir+0x60>
__vgic_v3_write_dir:689.6 (vgic-v3-sr.c) Sbepe u32 ║vid = vcpu_get_reg(vcpu, rt);
~ 0000e2e0: b9001fe0 str w0, [sp, #28]
__vgic_v3_write_dir:694.6 (vgic-v3-sr.c) Sbepe if (║!(vmcr & ICH_VMCR_EOIM_MASK))
~ 0000e2e4: 385e53a8 ldurb w8, [x29, #-27]
~ ┌──0000e2e8: 37080068 tbnz w8, #1, e2f4 <__vgic_v3_write_dir+0x78>
│
~ │┌─0000e2ec: 14000001 b e2f0 <__vgic_v3_write_dir+0x74> <- 0000e2e8(b.cc-succ)<fallthrough>
││
││ __vgic_v3_write_dir:695.3 (vgic-v3-sr.c) Sbepe ║return;
~ ┌────┼└>0000e2f0: 14000015 b e344 <__vgic_v3_write_dir+0xc8> <- 0000e2ec(b)<__vgic_v3_write_dir+0x74>
│ │
│ │ __vgic_v3_write_dir:698.6 (vgic-v3-sr.c) Sbepe if (║vid >= VGIC_MIN_LPI)
~ │ └─>0000e2f4: b9401fe8 ldr w8, [sp, #28] <- 0000e2e8(b.cc)<__vgic_v3_write_dir+0x78>
│ __vgic_v3_write_dir:698.6 (vgic-v3-sr.c) sbepe if (║vid >= VGIC_MIN_LPI)
~ │ 0000e2f8: 71400908 subs w8, w8, #0x2, lsl #12
~ │ ┌──0000e2fc: 54000063 b.cc e308 <__vgic_v3_write_dir+0x8c> // b.lo, b.ul, b.last
│ │
~ │ │┌─0000e300: 14000001 b e304 <__vgic_v3_write_dir+0x88> <- 0000e2fc(b.cc-succ)<fallthrough>
│ ││
│ ││ __vgic_v3_write_dir:699.3 (vgic-v3-sr.c) Sbepe ║return;
~ │ ┌──┼└>0000e304: 14000010 b e344 <__vgic_v3_write_dir+0xc8> <- 0000e300(b)<__vgic_v3_write_dir+0x88>
│ │ │
│ │ │ __vgic_v3_write_dir:701.32 (vgic-v3-sr.c) Sbepe lr = __vgic_v3_find_active_lr(║vcpu, vid, &lr_val);
~ │ │ └─>0000e308: f85e83a0 ldur x0, [x29, #-24] <- 0000e2fc(b.cc)<__vgic_v3_write_dir+0x8c>
│ │ __vgic_v3_write_dir:701.38 (vgic-v3-sr.c) sbepe lr = __vgic_v3_find_active_lr(vcpu, ║vid, &lr_val);
~ │ │ 0000e30c: b9401fe1 ldr w1, [sp, #28]
~ │ │ 0000e310: 910043e2 add x2, sp, #0x10
│ │ __vgic_v3_write_dir:701.7 (vgic-v3-sr.c) sbepe lr = ║__vgic_v3_find_active_lr(vcpu, vid, &lr_val);
~ │ │ 0000e314: 940002a7 bl edb0 <__vgic_v3_find_active_lr>
│ │
│ │ __vgic_v3_write_dir:701.5 (vgic-v3-sr.c) sbepe lr ║= __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
~ │ │ 0000e318: b9000fe0 str w0, [sp, #12] <- 0000e314(bl-succ)<return>
│ │ __vgic_v3_write_dir:702.6 (vgic-v3-sr.c) Sbepe if (║lr == -1) {
~ │ │ 0000e31c: b9400fe8 ldr w8, [sp, #12]
│ │ __vgic_v3_write_dir:702.6 (vgic-v3-sr.c) sbepe if (║lr == -1) {
~ │ │ 0000e320: 31000508 adds w8, w8, #0x1
~ │ │ ┌──0000e324: 54000081 b.ne e334 <__vgic_v3_write_dir+0xb8> // b.any
│ │ │
~ │ │ │┌─0000e328: 14000001 b e32c <__vgic_v3_write_dir+0xb0> <- 0000e324(b.cc-succ)<fallthrough>
│ │ ││
│ │ ││ __vgic_v3_write_dir:703.3 (vgic-v3-sr.c) Sbepe ║__vgic_v3_bump_eoicount();
~ │ │ │└>0000e32c: 940002d4 bl ee7c <__vgic_v3_bump_eoicount> <- 0000e328(b)<__vgic_v3_write_dir+0xb0>
│ │ │
│ │ │ __vgic_v3_write_dir:704.3 (vgic-v3-sr.c) Sbepe ║return;
~ │ │ ┌┼──0000e330: 14000005 b e344 <__vgic_v3_write_dir+0xc8> <- 0000e32c(bl-succ)<return>
│ │ ││
│ │ ││ __vgic_v3_write_dir:707.28 (vgic-v3-sr.c) Sbepe __vgic_v3_clear_active_lr(║lr, lr_val);
~ │ │ │└─>0000e334: b9400fe0 ldr w0, [sp, #12] <- 0000e324(b.cc)<__vgic_v3_write_dir+0xb8>
│ │ │ __vgic_v3_write_dir:707.32 (vgic-v3-sr.c) sbepe __vgic_v3_clear_active_lr(lr, ║lr_val);
~ │ │ │ 0000e338: f9400be1 ldr x1, [sp, #16]
│ │ │ __vgic_v3_write_dir:707.2 (vgic-v3-sr.c) sbepe ║__vgic_v3_clear_active_lr(lr, lr_val);
~ │ │ │ 0000e33c: 940002e4 bl eecc <__vgic_v3_clear_active_lr>
│ │ │
│ │ │ __vgic_v3_write_dir:708.1 (vgic-v3-sr.c) Sbepe ║}
~ │ │ │ ┌─0000e340: 14000001 b e344 <__vgic_v3_write_dir+0xc8> <- 0000e33c(bl-succ)<return>
│ │ │ │
~ └>└>└>└>0000e344: a9447bfd ldp x29, x30, [sp, #64] <- 0000e2f0(b)<__vgic_v3_write_dir+0xc8>,0000e304(b)<__vgic_v3_write_dir+0xc8>,0000e330(b)<__vgic_v3_write_dir+0xc8>,0000e340(b)<__vgic_v3_write_dir+0xc8>
~ 0000e348: 910143ff add sp, sp, #0x50
0000e288 CFA:r29+16 r29:c-16 r30:c-8
~ 0000e34c: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe27c 0xe350 (DW_OP_fbreg -0x18) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:687
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe27c 0xe350 (DW_OP_fbreg -0x1c) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:687
-rt param int (base type, DW_ATE_signed size:4) 0xe27c 0xe350 (DW_OP_breg31 0x20) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:687
-vid var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe27c 0xe350 (DW_OP_breg31 0x1c) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:689
-lr_val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe27c 0xe350 (DW_OP_breg31 0x10) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:690
-lr var int (base type, DW_ATE_signed size:4) 0xe27c 0xe350 (DW_OP_breg31 0xc) __vgic_v3_write_dir:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:691
**0000e350 <__vgic_v3_read_rpr>:
+ __vgic_v3_read_rpr params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe350 0xe3c4 (DW_OP_breg31 0x10)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe350 0xe3c4 (DW_OP_breg31 0xc)
+rt param int (base type, DW_ATE_signed size:4) 0xe350 0xe3c4 (DW_OP_breg31 0x8)
__vgic_v3_read_rpr:931.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe350 0xe3c4 (DW_OP_breg31 0x10) __vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:930
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe350 0xe3c4 (DW_OP_breg31 0xc) __vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:930
+rt param int (base type, DW_ATE_signed size:4) 0xe350 0xe3c4 (DW_OP_breg31 0x8) __vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:930
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe350 0xe3c4 (DW_OP_breg31 0x4) __vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:932
~ 0000e350: d10103ff sub sp, sp, #0x40
~ 0000e354: a9037bfd stp x29, x30, [sp, #48]
0000e350 CFA:r31 r29:u r30:u
~ 0000e358: 9100c3fd add x29, sp, #0x30
~ 0000e35c: f9000be0 str x0, [sp, #16]
~ 0000e360: b9000fe1 str w1, [sp, #12]
~ 0000e364: b9000be2 str w2, [sp, #8]
__vgic_v3_read_rpr:932.12 (vgic-v3-sr.c) SbePe u32 val = ║__vgic_v3_get_highest_active_priority();
~ 0000e368: 9400015a bl e8d0 <__vgic_v3_get_highest_active_priority>
__vgic_v3_read_rpr:932.6 (vgic-v3-sr.c) sbepe u32 ║val = __vgic_v3_get_highest_active_priority();
~ 0000e36c: b90007e0 str w0, [sp, #4] <- 0000e368(bl-succ)<return>
__vgic_v3_read_rpr:933.15 (vgic-v3-sr.c) Sbepe vcpu_set_reg(║vcpu, rt, val);
~ 0000e370: f9400be8 ldr x8, [sp, #16]
__vgic_v3_read_rpr:933.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, val);
~ 0000e374: b9400be9 ldr w9, [sp, #8]
__vgic_v3_read_rpr:933.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║val);
~ 0000e378: b94007ea ldr w10, [sp, #4]
~ 0000e37c: 2a0a03eb mov w11, w10
~ 0000e380: f81f83a8 stur x8, [x29, #-8]
~ 0000e384: 381f43a9 sturb w9, [x29, #-12]
~ 0000e388: f9000feb str x11, [sp, #24]
c: 0xe38c 0xe3b8 vcpu_set_reg inlined from __vgic_v3_read_rpr:933 (vgic-v3-sr.c) <a9171>:
c vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe38c 0xe3b8 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe38c 0xe3b8 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe38c 0xe3b8 (DW_OP_breg31 0x18) vcpu_set_reg(inlined):__vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~c 0000e38c: 385f43a9 ldurb w9, [x29, #-12]
c vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~c 0000e390: 71007d29 subs w9, w9, #0x1f
~c ┌───0000e394: 54000120 b.eq e3b8 <__vgic_v3_read_rpr+0x68> // b.none
│
~c │ ┌─0000e398: 14000001 b e39c <__vgic_v3_read_rpr+0x4c> <- 0000e394(b.cc-succ)<fallthrough>
│ │
c │ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~c │ └>0000e39c: f9400fe8 ldr x8, [sp, #24] <- 0000e398(b)<__vgic_v3_read_rpr+0x4c>
c │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~c │ 0000e3a0: f85f83a9 ldur x9, [x29, #-8]
c │ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~c │ 0000e3a4: 385f43aa ldurb w10, [x29, #-12]
~c │ 0000e3a8: 2a0a03eb mov w11, w10
c │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~c │ 0000e3ac: 8b0b0d29 add x9, x9, x11, lsl #3
c │ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~c │ 0000e3b0: f900b128 str x8, [x9, #352]
c │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~c │ ┌─0000e3b4: 14000001 b e3b8 <__vgic_v3_read_rpr+0x68>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe38c 0xe3b8 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe38c 0xe3b8 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe38c 0xe3b8 (DW_OP_breg31 0x18) vcpu_set_reg(inlined):__vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
│ │ __vgic_v3_read_rpr:934.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000e3b8: a9437bfd ldp x29, x30, [sp, #48] <- 0000e394(b.cc)<__vgic_v3_read_rpr+0x68>,0000e3b4(b)<__vgic_v3_read_rpr+0x68>
~ 0000e3bc: 910103ff add sp, sp, #0x40
0000e35c CFA:r29+16 r29:c-16 r30:c-8
~ 0000e3c0: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe350 0xe3c4 (DW_OP_breg31 0x10) __vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:930
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe350 0xe3c4 (DW_OP_breg31 0xc) __vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:930
-rt param int (base type, DW_ATE_signed size:4) 0xe350 0xe3c4 (DW_OP_breg31 0x8) __vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:930
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe350 0xe3c4 (DW_OP_breg31 0x4) __vgic_v3_read_rpr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:932
**0000e3c4 <__vgic_v3_read_ctlr>:
+ __vgic_v3_read_ctlr params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x20)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x1c)
+rt param int (base type, DW_ATE_signed size:4) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x18)
__vgic_v3_read_ctlr:937.0 (vgic-v3-sr.c) Sbepe ║{
0000e3c4 CFA:r31
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x20) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:936
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x1c) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:936
+rt param int (base type, DW_ATE_signed size:4) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x18) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:936
+vtr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x14) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:938
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x10) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:938
~ 0000e3c4: d10103ff sub sp, sp, #0x40
~ 0000e3c8: f90013e0 str x0, [sp, #32]
~ 0000e3cc: b9001fe1 str w1, [sp, #28]
~ 0000e3d0: b9001be2 str w2, [sp, #24]
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe3d4 0xe3e8 (DW_OP_fbreg 0x8) lexblock:__vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:940
~ 0000e3d4: d53ccb28 mrs x8, s3_4_c12_c11_1
__vgic_v3_read_ctlr:940.8 (vgic-v3-sr.c) SbePe vtr = ║read_gicreg(ICH_VTR_EL2);
~ 0000e3d8: f90007e8 str x8, [sp, #8]
~ 0000e3dc: f94007e8 ldr x8, [sp, #8]
~ 0000e3e0: f90003e8 str x8, [sp]
~ 0000e3e4: f94003e8 ldr x8, [sp]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe3d4 0xe3e8 (DW_OP_fbreg 0x8) lexblock:__vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:940
__vgic_v3_read_ctlr:940.6 (vgic-v3-sr.c) sbepe vtr ║= read_gicreg(ICH_VTR_EL2);
~ 0000e3e8: b90017e8 str w8, [sp, #20]
__vgic_v3_read_ctlr:942.10 (vgic-v3-sr.c) Sbepe val = ((║vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
~ 0000e3ec: b94017e8 ldr w8, [sp, #20]
__vgic_v3_read_ctlr:942.26 (vgic-v3-sr.c) sbepe val = ((vtr >> 29) & 7) ║<< ICC_CTLR_EL1_PRI_BITS_SHIFT;
~ 0000e3f0: 53157d08 lsr w8, w8, #21
__vgic_v3_read_ctlr:942.14 (vgic-v3-sr.c) sbepe val = ((vtr ║>> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
~ 0000e3f4: 12180908 and w8, w8, #0x700
__vgic_v3_read_ctlr:942.6 (vgic-v3-sr.c) sbepe val ║= ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
~ 0000e3f8: b90013e8 str w8, [sp, #16]
__vgic_v3_read_ctlr:944.11 (vgic-v3-sr.c) Sbepe val |= ((║vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
~ 0000e3fc: b94017e8 ldr w8, [sp, #20]
__vgic_v3_read_ctlr:944.22 (vgic-v3-sr.c) sbepe val |= ((vtr >> 23) ║& 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
~ 0000e400: 53176508 ubfx w8, w8, #23, #3
__vgic_v3_read_ctlr:944.6 (vgic-v3-sr.c) sbepe val ║|= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
~ 0000e404: b94013e9 ldr w9, [sp, #16]
~ 0000e408: 2a082d28 orr w8, w9, w8, lsl #11
~ 0000e40c: b90013e8 str w8, [sp, #16]
__vgic_v3_read_ctlr:946.11 (vgic-v3-sr.c) Sbepe val |= ((║vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT;
~ 0000e410: b94017e8 ldr w8, [sp, #20]
__vgic_v3_read_ctlr:946.22 (vgic-v3-sr.c) sbepe val |= ((vtr >> 22) ║& 1) << ICC_CTLR_EL1_SEIS_SHIFT;
~ 0000e414: 53165908 ubfx w8, w8, #22, #1
__vgic_v3_read_ctlr:946.6 (vgic-v3-sr.c) sbepe val ║|= ((vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT;
~ 0000e418: b94013e9 ldr w9, [sp, #16]
~ 0000e41c: 2a083928 orr w8, w9, w8, lsl #14
~ 0000e420: b90013e8 str w8, [sp, #16]
__vgic_v3_read_ctlr:948.11 (vgic-v3-sr.c) Sbepe val |= ((║vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
~ 0000e424: b94017e8 ldr w8, [sp, #20]
__vgic_v3_read_ctlr:948.22 (vgic-v3-sr.c) sbepe val |= ((vtr >> 21) ║& 1) << ICC_CTLR_EL1_A3V_SHIFT;
~ 0000e428: 53155508 ubfx w8, w8, #21, #1
__vgic_v3_read_ctlr:948.6 (vgic-v3-sr.c) sbepe val ║|= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
~ 0000e42c: b94013e9 ldr w9, [sp, #16]
~ 0000e430: 2a083d28 orr w8, w9, w8, lsl #15
~ 0000e434: b90013e8 str w8, [sp, #16]
__vgic_v3_read_ctlr:950.11 (vgic-v3-sr.c) Sbepe val |= ((║vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
~ 0000e438: b9401fe8 ldr w8, [sp, #28]
__vgic_v3_read_ctlr:950.16 (vgic-v3-sr.c) sbepe val |= ((vmcr ║& ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
~ 0000e43c: 12170108 and w8, w8, #0x200
__vgic_v3_read_ctlr:950.6 (vgic-v3-sr.c) sbepe val ║|= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
~ 0000e440: b94013e9 ldr w9, [sp, #16]
~ 0000e444: 2a482128 orr w8, w9, w8, lsr #8
~ 0000e448: b90013e8 str w8, [sp, #16]
__vgic_v3_read_ctlr:952.10 (vgic-v3-sr.c) Sbepe val |= (║vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
~ 0000e44c: b9401fe8 ldr w8, [sp, #28]
__vgic_v3_read_ctlr:952.15 (vgic-v3-sr.c) sbepe val |= (vmcr ║& ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
~ 0000e450: 121c0108 and w8, w8, #0x10
__vgic_v3_read_ctlr:952.6 (vgic-v3-sr.c) sbepe val ║|= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
~ 0000e454: b94013e9 ldr w9, [sp, #16]
~ 0000e458: 2a481128 orr w8, w9, w8, lsr #4
~ 0000e45c: b90013e8 str w8, [sp, #16]
__vgic_v3_read_ctlr:954.15 (vgic-v3-sr.c) Sbepe vcpu_set_reg(║vcpu, rt, val);
~ 0000e460: f94013ea ldr x10, [sp, #32]
__vgic_v3_read_ctlr:954.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, val);
~ 0000e464: b9401be8 ldr w8, [sp, #24]
__vgic_v3_read_ctlr:954.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║val);
~ 0000e468: b94013e9 ldr w9, [sp, #16]
~ 0000e46c: 2a0903eb mov w11, w9
~ 0000e470: f9001fea str x10, [sp, #56]
~ 0000e474: 3900d3e8 strb w8, [sp, #52]
~ 0000e478: f90017eb str x11, [sp, #40]
d: 0xe47c 0xe4a8 vcpu_set_reg inlined from __vgic_v3_read_ctlr:954 (vgic-v3-sr.c) <a921e>:
d vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe47c 0xe4a8 (DW_OP_fbreg 0x38) vcpu_set_reg(inlined):__vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe47c 0xe4a8 (DW_OP_fbreg 0x34) vcpu_set_reg(inlined):__vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe47c 0xe4a8 (DW_OP_fbreg 0x28) vcpu_set_reg(inlined):__vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~d 0000e47c: 3940d3e8 ldrb w8, [sp, #52]
d vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~d 0000e480: 71007d08 subs w8, w8, #0x1f
~d ┌───0000e484: 54000120 b.eq e4a8 <__vgic_v3_read_ctlr+0xe4> // b.none
│
~d │ ┌─0000e488: 14000001 b e48c <__vgic_v3_read_ctlr+0xc8> <- 0000e484(b.cc-succ)<fallthrough>
│ │
d │ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~d │ └>0000e48c: f94017e8 ldr x8, [sp, #40] <- 0000e488(b)<__vgic_v3_read_ctlr+0xc8>
d │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~d │ 0000e490: f9401fe9 ldr x9, [sp, #56]
d │ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~d │ 0000e494: 3940d3ea ldrb w10, [sp, #52]
~d │ 0000e498: 2a0a03eb mov w11, w10
d │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~d │ 0000e49c: 8b0b0d29 add x9, x9, x11, lsl #3
d │ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~d │ 0000e4a0: f900b128 str x8, [x9, #352]
d │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~d │ ┌─0000e4a4: 14000001 b e4a8 <__vgic_v3_read_ctlr+0xe4>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe47c 0xe4a8 (DW_OP_fbreg 0x38) vcpu_set_reg(inlined):__vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe47c 0xe4a8 (DW_OP_fbreg 0x34) vcpu_set_reg(inlined):__vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe47c 0xe4a8 (DW_OP_fbreg 0x28) vcpu_set_reg(inlined):__vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
│ │ __vgic_v3_read_ctlr:955.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000e4a8: 910103ff add sp, sp, #0x40 <- 0000e484(b.cc)<__vgic_v3_read_ctlr+0xe4>,0000e4a4(b)<__vgic_v3_read_ctlr+0xe4>
0000e3c8 CFA:r31+64
~ 0000e4ac: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x20) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:936
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x1c) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:936
-rt param int (base type, DW_ATE_signed size:4) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x18) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:936
-vtr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x14) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:938
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe3c4 0xe4b0 (DW_OP_fbreg 0x10) __vgic_v3_read_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:938
**0000e4b0 <__vgic_v3_write_ctlr>:
+ __vgic_v3_write_ctlr params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe4b0 0xe58c (DW_OP_fbreg 0x28)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe4b0 0xe58c (DW_OP_fbreg 0x24)
+rt param int (base type, DW_ATE_signed size:4) 0xe4b0 0xe58c (DW_OP_fbreg 0x20)
__vgic_v3_write_ctlr:958.0 (vgic-v3-sr.c) Sbepe ║{
0000e4b0 CFA:r31
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe4b0 0xe58c (DW_OP_fbreg 0x28) __vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:957
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe4b0 0xe58c (DW_OP_fbreg 0x24) __vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:957
+rt param int (base type, DW_ATE_signed size:4) 0xe4b0 0xe58c (DW_OP_fbreg 0x20) __vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:957
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe4b0 0xe58c (DW_OP_fbreg 0x1c) __vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:959
~ 0000e4b0: d10103ff sub sp, sp, #0x40
~ 0000e4b4: f90017e0 str x0, [sp, #40]
~ 0000e4b8: b90027e1 str w1, [sp, #36]
~ 0000e4bc: b90023e2 str w2, [sp, #32]
__vgic_v3_write_ctlr:959.25 (vgic-v3-sr.c) SbePe u32 val = vcpu_get_reg(║vcpu, rt);
~ 0000e4c0: f94017e8 ldr x8, [sp, #40]
__vgic_v3_write_ctlr:959.31 (vgic-v3-sr.c) sbepe u32 val = vcpu_get_reg(vcpu, ║rt);
~ 0000e4c4: b94023e9 ldr w9, [sp, #32]
~ 0000e4c8: f9001fe8 str x8, [sp, #56]
~ 0000e4cc: 3900d3e9 strb w9, [sp, #52]
e: 0xe4d0 0xe508 vcpu_get_reg inlined from __vgic_v3_write_ctlr:959 (vgic-v3-sr.c) <a929f>:
e vcpu_get_reg:166.10 (kvm_emulate.h) Sbepe return (║reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe4d0 0xe508 (DW_OP_fbreg 0x38) vcpu_get_reg(inlined):__vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe4d0 0xe508 (DW_OP_fbreg 0x34) vcpu_get_reg(inlined):__vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~e 0000e4d0: 3940d3e9 ldrb w9, [sp, #52]
e vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~e 0000e4d4: 71007d29 subs w9, w9, #0x1f
~e ┌──0000e4d8: 540000a1 b.ne e4ec <__vgic_v3_write_ctlr+0x3c> // b.any
│
~e │┌─0000e4dc: 14000001 b e4e0 <__vgic_v3_write_ctlr+0x30> <- 0000e4d8(b.cc-succ)<fallthrough>
││
~e │└>0000e4e0: aa1f03e0 mov x0, xzr <- 0000e4dc(b)<__vgic_v3_write_ctlr+0x30>
~e │ 0000e4e4: f90007e0 str x0, [sp, #8]
e │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~e ┌┼──0000e4e8: 14000008 b e508 <__vgic_v3_write_ctlr+0x58>
││
e ││ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~e │└─>0000e4ec: f9401fe8 ldr x8, [sp, #56] <- 0000e4d8(b.cc)<__vgic_v3_write_ctlr+0x3c>
e │ vcpu_get_reg:166.56 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[║reg_num];
~e │ 0000e4f0: 3940d3e9 ldrb w9, [sp, #52]
~e │ 0000e4f4: 2a0903ea mov w10, w9
e │ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~e │ 0000e4f8: 8b0a0d08 add x8, x8, x10, lsl #3
~e │ 0000e4fc: f940b108 ldr x8, [x8, #352]
~e │ 0000e500: f90007e8 str x8, [sp, #8]
e │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~e │ ┌─0000e504: 14000001 b e508 <__vgic_v3_write_ctlr+0x58>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe4d0 0xe508 (DW_OP_fbreg 0x38) vcpu_get_reg(inlined):__vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe4d0 0xe508 (DW_OP_fbreg 0x34) vcpu_get_reg(inlined):__vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
~ └>└>0000e508: f94007e0 ldr x0, [sp, #8] <- 0000e4e8(b)<__vgic_v3_write_ctlr+0x58>,0000e504(b)<__vgic_v3_write_ctlr+0x58>
__vgic_v3_write_ctlr:959.6 (vgic-v3-sr.c) Sbepe u32 ║val = vcpu_get_reg(vcpu, rt);
~ 0000e50c: b9001fe0 str w0, [sp, #28]
__vgic_v3_write_ctlr:961.6 (vgic-v3-sr.c) Sbepe if (║val & ICC_CTLR_EL1_CBPR_MASK)
~ 0000e510: 394073e8 ldrb w8, [sp, #28]
~ ┌──0000e514: 360000c8 tbz w8, #0, e52c <__vgic_v3_write_ctlr+0x7c>
│
~ │┌─0000e518: 14000001 b e51c <__vgic_v3_write_ctlr+0x6c> <- 0000e514(b.cc-succ)<fallthrough>
││
││ __vgic_v3_write_ctlr:962.8 (vgic-v3-sr.c) Sbepe vmcr ║|= ICH_VMCR_CBPR_MASK;
~ │└>0000e51c: b94027e8 ldr w8, [sp, #36] <- 0000e518(b)<__vgic_v3_write_ctlr+0x6c>
~ │ 0000e520: 321c0108 orr w8, w8, #0x10
~ │ 0000e524: b90027e8 str w8, [sp, #36]
│ __vgic_v3_write_ctlr:962.3 (vgic-v3-sr.c) sbepe ║vmcr |= ICH_VMCR_CBPR_MASK;
~ ┌┼──0000e528: 14000005 b e53c <__vgic_v3_write_ctlr+0x8c>
││
││ __vgic_v3_write_ctlr:964.8 (vgic-v3-sr.c) Sbepe vmcr ║&= ~ICH_VMCR_CBPR_MASK;
~ │└─>0000e52c: b94027e8 ldr w8, [sp, #36] <- 0000e514(b.cc)<__vgic_v3_write_ctlr+0x7c>
~ │ 0000e530: 121b7908 and w8, w8, #0xffffffef
~ │ 0000e534: b90027e8 str w8, [sp, #36]
~ │ ┌─0000e538: 14000001 b e53c <__vgic_v3_write_ctlr+0x8c>
│ │
│ │ __vgic_v3_write_ctlr:966.6 (vgic-v3-sr.c) Sbepe if (║val & ICC_CTLR_EL1_EOImode_MASK)
~ └>└>0000e53c: 394073e8 ldrb w8, [sp, #28] <- 0000e528(b)<__vgic_v3_write_ctlr+0x8c>,0000e538(b)<__vgic_v3_write_ctlr+0x8c>
~ ┌──0000e540: 360800c8 tbz w8, #1, e558 <__vgic_v3_write_ctlr+0xa8>
│
~ │┌─0000e544: 14000001 b e548 <__vgic_v3_write_ctlr+0x98> <- 0000e540(b.cc-succ)<fallthrough>
││
││ __vgic_v3_write_ctlr:967.8 (vgic-v3-sr.c) Sbepe vmcr ║|= ICH_VMCR_EOIM_MASK;
~ │└>0000e548: b94027e8 ldr w8, [sp, #36] <- 0000e544(b)<__vgic_v3_write_ctlr+0x98>
~ │ 0000e54c: 32170108 orr w8, w8, #0x200
~ │ 0000e550: b90027e8 str w8, [sp, #36]
│ __vgic_v3_write_ctlr:967.3 (vgic-v3-sr.c) sbepe ║vmcr |= ICH_VMCR_EOIM_MASK;
~ ┌──┼──0000e554: 14000005 b e568 <__vgic_v3_write_ctlr+0xb8>
│ │
│ │ __vgic_v3_write_ctlr:969.8 (vgic-v3-sr.c) Sbepe vmcr ║&= ~ICH_VMCR_EOIM_MASK;
~ │ └─>0000e558: b94027e8 ldr w8, [sp, #36] <- 0000e540(b.cc)<__vgic_v3_write_ctlr+0xa8>
~ │ 0000e55c: 12167908 and w8, w8, #0xfffffdff
~ │ 0000e560: b90027e8 str w8, [sp, #36]
~ │ ┌─0000e564: 14000001 b e568 <__vgic_v3_write_ctlr+0xb8>
│ │
│ │ __vgic_v3_write_ctlr:971.2 (vgic-v3-sr.c) Sbepe ║write_gicreg(vmcr, ICH_VMCR_EL2);
~ └>┌─└>0000e568: 14000001 b e56c <__vgic_v3_write_ctlr+0xbc> <- 0000e554(b)<__vgic_v3_write_ctlr+0xb8>,0000e564(b)<__vgic_v3_write_ctlr+0xb8>
│
│ __vgic_v3_write_ctlr:971.2 (vgic-v3-sr.c) sbepe ║write_gicreg(vmcr, ICH_VMCR_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe56c 0xe584 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:971
~ └──>0000e56c: b94027e8 ldr w8, [sp, #36] <- 0000e568(b)<__vgic_v3_write_ctlr+0xbc>
~ 0000e570: 2a0803e9 mov w9, w8
~ 0000e574: f9000be9 str x9, [sp, #16]
~ 0000e578: f9400be9 ldr x9, [sp, #16]
~ 0000e57c: d51ccbe9 msr s3_4_c12_c11_7, x9
~ ┌─0000e580: 14000001 b e584 <__vgic_v3_write_ctlr+0xd4>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe56c 0xe584 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:971
│
│ __vgic_v3_write_ctlr:972.1 (vgic-v3-sr.c) Sbepe ║}
~ └>0000e584: 910103ff add sp, sp, #0x40 <- 0000e580(b)<__vgic_v3_write_ctlr+0xd4>
0000e4b4 CFA:r31+64
~ 0000e588: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe4b0 0xe58c (DW_OP_fbreg 0x28) __vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:957
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe4b0 0xe58c (DW_OP_fbreg 0x24) __vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:957
-rt param int (base type, DW_ATE_signed size:4) 0xe4b0 0xe58c (DW_OP_fbreg 0x20) __vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:957
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe4b0 0xe58c (DW_OP_fbreg 0x1c) __vgic_v3_write_ctlr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:959
**0000e58c <__vgic_v3_read_pmr>:
+ __vgic_v3_read_pmr params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe58c 0xe604 (DW_OP_fbreg 0x10)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe58c 0xe604 (DW_OP_fbreg 0xc)
+rt param int (base type, DW_ATE_signed size:4) 0xe58c 0xe604 (DW_OP_fbreg 0x8)
__vgic_v3_read_pmr:912.0 (vgic-v3-sr.c) Sbepe ║{
0000e58c CFA:r31
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe58c 0xe604 (DW_OP_fbreg 0x10) __vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:911
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe58c 0xe604 (DW_OP_fbreg 0xc) __vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:911
+rt param int (base type, DW_ATE_signed size:4) 0xe58c 0xe604 (DW_OP_fbreg 0x8) __vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:911
~ 0000e58c: d100c3ff sub sp, sp, #0x30
~ 0000e590: f9000be0 str x0, [sp, #16]
~ 0000e594: b9000fe1 str w1, [sp, #12]
~ 0000e598: b9000be2 str w2, [sp, #8]
__vgic_v3_read_pmr:913.7 (vgic-v3-sr.c) SbePe vmcr ║&= ICH_VMCR_PMR_MASK;
~ 0000e59c: 39403fe8 ldrb w8, [sp, #15]
~ 0000e5a0: 53081d08 lsl w8, w8, #24
~ 0000e5a4: 2a0803e0 mov w0, w8
~ 0000e5a8: b9000fe0 str w0, [sp, #12]
__vgic_v3_read_pmr:914.7 (vgic-v3-sr.c) Sbepe vmcr ║>>= ICH_VMCR_PMR_SHIFT;
~ 0000e5ac: 39403fe8 ldrb w8, [sp, #15]
~ 0000e5b0: b9000fe8 str w8, [sp, #12]
__vgic_v3_read_pmr:915.15 (vgic-v3-sr.c) Sbepe vcpu_set_reg(║vcpu, rt, vmcr);
~ 0000e5b4: f9400be9 ldr x9, [sp, #16]
__vgic_v3_read_pmr:915.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, vmcr);
~ 0000e5b8: b9400be8 ldr w8, [sp, #8]
__vgic_v3_read_pmr:915.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║vmcr);
~ 0000e5bc: b9400fea ldr w10, [sp, #12]
~ 0000e5c0: 2a0a03eb mov w11, w10
~ 0000e5c4: f90017e9 str x9, [sp, #40]
~ 0000e5c8: 390093e8 strb w8, [sp, #36]
~ 0000e5cc: f9000feb str x11, [sp, #24]
f: 0xe5d0 0xe5fc vcpu_set_reg inlined from __vgic_v3_read_pmr:915 (vgic-v3-sr.c) <a9326>:
f vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe5d0 0xe5fc (DW_OP_fbreg 0x28) vcpu_set_reg(inlined):__vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe5d0 0xe5fc (DW_OP_fbreg 0x24) vcpu_set_reg(inlined):__vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe5d0 0xe5fc (DW_OP_fbreg 0x18) vcpu_set_reg(inlined):__vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~f 0000e5d0: 394093e8 ldrb w8, [sp, #36]
f vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~f 0000e5d4: 71007d08 subs w8, w8, #0x1f
~f ┌───0000e5d8: 54000120 b.eq e5fc <__vgic_v3_read_pmr+0x70> // b.none
│
~f │ ┌─0000e5dc: 14000001 b e5e0 <__vgic_v3_read_pmr+0x54> <- 0000e5d8(b.cc-succ)<fallthrough>
│ │
f │ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~f │ └>0000e5e0: f9400fe8 ldr x8, [sp, #24] <- 0000e5dc(b)<__vgic_v3_read_pmr+0x54>
f │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~f │ 0000e5e4: f94017e9 ldr x9, [sp, #40]
f │ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~f │ 0000e5e8: 394093ea ldrb w10, [sp, #36]
~f │ 0000e5ec: 2a0a03eb mov w11, w10
f │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~f │ 0000e5f0: 8b0b0d29 add x9, x9, x11, lsl #3
f │ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~f │ 0000e5f4: f900b128 str x8, [x9, #352]
f │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~f │ ┌─0000e5f8: 14000001 b e5fc <__vgic_v3_read_pmr+0x70>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe5d0 0xe5fc (DW_OP_fbreg 0x28) vcpu_set_reg(inlined):__vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe5d0 0xe5fc (DW_OP_fbreg 0x24) vcpu_set_reg(inlined):__vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe5d0 0xe5fc (DW_OP_fbreg 0x18) vcpu_set_reg(inlined):__vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
│ │ __vgic_v3_read_pmr:916.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000e5fc: 9100c3ff add sp, sp, #0x30 <- 0000e5d8(b.cc)<__vgic_v3_read_pmr+0x70>,0000e5f8(b)<__vgic_v3_read_pmr+0x70>
0000e590 CFA:r31+48
~ 0000e600: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe58c 0xe604 (DW_OP_fbreg 0x10) __vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:911
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe58c 0xe604 (DW_OP_fbreg 0xc) __vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:911
-rt param int (base type, DW_ATE_signed size:4) 0xe58c 0xe604 (DW_OP_fbreg 0x8) __vgic_v3_read_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:911
**0000e604 <__vgic_v3_write_pmr>:
+ __vgic_v3_write_pmr params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe604 0xe6c4 (DW_OP_fbreg 0x28)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe604 0xe6c4 (DW_OP_fbreg 0x24)
+rt param int (base type, DW_ATE_signed size:4) 0xe604 0xe6c4 (DW_OP_fbreg 0x20)
__vgic_v3_write_pmr:919.0 (vgic-v3-sr.c) Sbepe ║{
0000e604 CFA:r31
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe604 0xe6c4 (DW_OP_fbreg 0x28) __vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:918
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe604 0xe6c4 (DW_OP_fbreg 0x24) __vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:918
+rt param int (base type, DW_ATE_signed size:4) 0xe604 0xe6c4 (DW_OP_fbreg 0x20) __vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:918
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe604 0xe6c4 (DW_OP_fbreg 0x1c) __vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:920
~ 0000e604: d10103ff sub sp, sp, #0x40
~ 0000e608: f90017e0 str x0, [sp, #40]
~ 0000e60c: b90027e1 str w1, [sp, #36]
~ 0000e610: b90023e2 str w2, [sp, #32]
__vgic_v3_write_pmr:920.25 (vgic-v3-sr.c) SbePe u32 val = vcpu_get_reg(║vcpu, rt);
~ 0000e614: f94017e8 ldr x8, [sp, #40]
__vgic_v3_write_pmr:920.31 (vgic-v3-sr.c) sbepe u32 val = vcpu_get_reg(vcpu, ║rt);
~ 0000e618: b94023e9 ldr w9, [sp, #32]
~ 0000e61c: f9001fe8 str x8, [sp, #56]
~ 0000e620: 3900d3e9 strb w9, [sp, #52]
g: 0xe624 0xe65c vcpu_get_reg inlined from __vgic_v3_write_pmr:920 (vgic-v3-sr.c) <a93a7>:
g vcpu_get_reg:166.10 (kvm_emulate.h) Sbepe return (║reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe624 0xe65c (DW_OP_fbreg 0x38) vcpu_get_reg(inlined):__vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe624 0xe65c (DW_OP_fbreg 0x34) vcpu_get_reg(inlined):__vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~g 0000e624: 3940d3e9 ldrb w9, [sp, #52]
g vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~g 0000e628: 71007d29 subs w9, w9, #0x1f
~g ┌──0000e62c: 540000a1 b.ne e640 <__vgic_v3_write_pmr+0x3c> // b.any
│
~g │┌─0000e630: 14000001 b e634 <__vgic_v3_write_pmr+0x30> <- 0000e62c(b.cc-succ)<fallthrough>
││
~g │└>0000e634: aa1f03e0 mov x0, xzr <- 0000e630(b)<__vgic_v3_write_pmr+0x30>
~g │ 0000e638: f90007e0 str x0, [sp, #8]
g │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~g ┌┼──0000e63c: 14000008 b e65c <__vgic_v3_write_pmr+0x58>
││
g ││ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~g │└─>0000e640: f9401fe8 ldr x8, [sp, #56] <- 0000e62c(b.cc)<__vgic_v3_write_pmr+0x3c>
g │ vcpu_get_reg:166.56 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[║reg_num];
~g │ 0000e644: 3940d3e9 ldrb w9, [sp, #52]
~g │ 0000e648: 2a0903ea mov w10, w9
g │ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~g │ 0000e64c: 8b0a0d08 add x8, x8, x10, lsl #3
~g │ 0000e650: f940b108 ldr x8, [x8, #352]
~g │ 0000e654: f90007e8 str x8, [sp, #8]
g │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~g │ ┌─0000e658: 14000001 b e65c <__vgic_v3_write_pmr+0x58>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe624 0xe65c (DW_OP_fbreg 0x38) vcpu_get_reg(inlined):__vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe624 0xe65c (DW_OP_fbreg 0x34) vcpu_get_reg(inlined):__vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
~ └>└>0000e65c: f94007e0 ldr x0, [sp, #8] <- 0000e63c(b)<__vgic_v3_write_pmr+0x58>,0000e658(b)<__vgic_v3_write_pmr+0x58>
__vgic_v3_write_pmr:920.6 (vgic-v3-sr.c) Sbepe u32 ║val = vcpu_get_reg(vcpu, rt);
~ 0000e660: b9001fe0 str w0, [sp, #28]
__vgic_v3_write_pmr:922.6 (vgic-v3-sr.c) Sbepe val ║<<= ICH_VMCR_PMR_SHIFT;
~ 0000e664: b9401fe8 ldr w8, [sp, #28]
~ 0000e668: 53081d08 lsl w8, w8, #24
~ 0000e66c: b9001fe8 str w8, [sp, #28]
__vgic_v3_write_pmr:923.6 (vgic-v3-sr.c) Sbepe val ║&= ICH_VMCR_PMR_MASK;
~ 0000e670: 39407fe8 ldrb w8, [sp, #31]
~ 0000e674: 53081d08 lsl w8, w8, #24
~ 0000e678: 2a0803e1 mov w1, w8
~ 0000e67c: b9001fe1 str w1, [sp, #28]
__vgic_v3_write_pmr:924.7 (vgic-v3-sr.c) Sbepe vmcr ║&= ~ICH_VMCR_PMR_MASK;
~ 0000e680: b94027e8 ldr w8, [sp, #36]
~ 0000e684: 12005d08 and w8, w8, #0xffffff
~ 0000e688: 2a0803e2 mov w2, w8
~ 0000e68c: b90027e2 str w2, [sp, #36]
__vgic_v3_write_pmr:925.10 (vgic-v3-sr.c) Sbepe vmcr |= ║val;
~ 0000e690: b9401fe8 ldr w8, [sp, #28]
__vgic_v3_write_pmr:925.7 (vgic-v3-sr.c) sbepe vmcr ║|= val;
~ 0000e694: b94027e9 ldr w9, [sp, #36]
~ 0000e698: 2a080128 orr w8, w9, w8
~ 0000e69c: b90027e8 str w8, [sp, #36]
__vgic_v3_write_pmr:927.2 (vgic-v3-sr.c) Sbepe ║write_gicreg(vmcr, ICH_VMCR_EL2);
~ ┌─0000e6a0: 14000001 b e6a4 <__vgic_v3_write_pmr+0xa0>
│
│ __vgic_v3_write_pmr:927.2 (vgic-v3-sr.c) sbepe ║write_gicreg(vmcr, ICH_VMCR_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe6a4 0xe6bc (DW_OP_fbreg 0x10) lexblock:__vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:927
~ └>0000e6a4: b94027e8 ldr w8, [sp, #36] <- 0000e6a0(b)<__vgic_v3_write_pmr+0xa0>
~ 0000e6a8: 2a0803e9 mov w9, w8
~ 0000e6ac: f9000be9 str x9, [sp, #16]
~ 0000e6b0: f9400be9 ldr x9, [sp, #16]
~ 0000e6b4: d51ccbe9 msr s3_4_c12_c11_7, x9
~ ┌─0000e6b8: 14000001 b e6bc <__vgic_v3_write_pmr+0xb8>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe6a4 0xe6bc (DW_OP_fbreg 0x10) lexblock:__vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:927
│
│ __vgic_v3_write_pmr:928.1 (vgic-v3-sr.c) Sbepe ║}
~ └>0000e6bc: 910103ff add sp, sp, #0x40 <- 0000e6b8(b)<__vgic_v3_write_pmr+0xb8>
0000e608 CFA:r31+64
~ 0000e6c0: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe604 0xe6c4 (DW_OP_fbreg 0x28) __vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:918
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe604 0xe6c4 (DW_OP_fbreg 0x24) __vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:918
-rt param int (base type, DW_ATE_signed size:4) 0xe604 0xe6c4 (DW_OP_fbreg 0x20) __vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:918
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe604 0xe6c4 (DW_OP_fbreg 0x1c) __vgic_v3_write_pmr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:920
**0000e6c4 <kvm_skip_instr>:
+ kvm_skip_instr params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe6c4 0xe758 (DW_OP_breg31 0x0)
kvm_skip_instr:19.0 (adjust_pc.h) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe6c4 0xe758 (DW_OP_breg31 0x0) kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:18
~ 0000e6c4: d10103ff sub sp, sp, #0x40 <- 0000d7d4(bl)<kvm_skip_instr>
~ 0000e6c8: a9037bfd stp x29, x30, [sp, #48]
0000e6c4 CFA:r31 r29:u r30:u
~ 0000e6cc: 9100c3fd add x29, sp, #0x30
~ 0000e6d0: f90003e0 str x0, [sp]
kvm_skip_instr:20.25 (adjust_pc.h) SbePe if (vcpu_mode_is_32bit(║vcpu)) {
~ 0000e6d4: f94003e8 ldr x8, [sp]
~ 0000e6d8: f90007e8 str x8, [sp, #8]
h: 0xe6dc 0xe6e8 vcpu_mode_is_32bit inlined from kvm_skip_instr:20 (adjust_pc.h) <a940e>:
h vcpu_mode_is_32bit:142.23 (kvm_emulate.h) Sbepe return !!(*vcpu_cpsr(║vcpu) & PSR_MODE32_BIT);
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe6dc 0xe6e8 (DW_OP_breg31 0x8) vcpu_mode_is_32bit(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~h 0000e6dc: f94007e8 ldr x8, [sp, #8]
~h 0000e6e0: f9000be8 str x8, [sp, #16]
i: 0xe6e4 0xe6e8 vcpu_cpsr inlined from vcpu_mode_is_32bit:142 (kvm_emulate.h) <a942a>:<a940e>:
hi vcpu_cpsr:137.27 (kvm_emulate.h) Sbepe return (unsigned long *)&║vcpu_gp_regs(vcpu)->pstate;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe6e4 0xe6e8 (DW_OP_breg31 0x10) vcpu_cpsr(inlined):vcpu_mode_is_32bit(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~hi 0000e6e4: f9400be8 ldr x8, [sp, #16]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe6dc 0xe6e8 (DW_OP_breg31 0x8) vcpu_mode_is_32bit(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe6e4 0xe6e8 (DW_OP_breg31 0x10) vcpu_cpsr(inlined):vcpu_mode_is_32bit(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
kvm_skip_instr:20.6 (adjust_pc.h) Sbepe if (║vcpu_mode_is_32bit(vcpu)) {
~ 0000e6e8: 3949a109 ldrb w9, [x8, #616]
~ ┌──0000e6ec: 362000a9 tbz w9, #4, e700 <kvm_skip_instr+0x3c>
│
~ │┌─0000e6f0: 14000001 b e6f4 <kvm_skip_instr+0x30> <- 0000e6ec(b.cc-succ)<fallthrough>
││
││ kvm_skip_instr:21.20 (adjust_pc.h) Sbepe kvm_skip_instr32(║vcpu);
~ │└>0000e6f4: f94003e0 ldr x0, [sp] <- 0000e6f0(b)<kvm_skip_instr+0x30>
│ kvm_skip_instr:21.3 (adjust_pc.h) sbepe ║kvm_skip_instr32(vcpu);
~ │ 0000e6f8: 940002ba bl f1e0 <kvm_skip_instr32>
│
│ kvm_skip_instr:22.2 (adjust_pc.h) Sbepe ║} else {
~ ┌┼──0000e6fc: 1400000e b e734 <kvm_skip_instr+0x70> <- 0000e6f8(bl-succ)<return>
││
││ kvm_skip_instr:23.12 (adjust_pc.h) Sbepe *vcpu_pc(║vcpu) += 4;
~ │└─>0000e700: f94003e8 ldr x8, [sp] <- 0000e6ec(b.cc)<kvm_skip_instr+0x3c>
~ │ 0000e704: f81f83a8 stur x8, [x29, #-8]
j: 0xe708 0xe70c vcpu_pc inlined from kvm_skip_instr:23 (adjust_pc.h) <a9448>:
j │ vcpu_pc:132.27 (kvm_emulate.h) Sbepe return (unsigned long *)&║vcpu_gp_regs(vcpu)->pc;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe708 0xe70c (DW_OP_fbreg -0x8) vcpu_pc(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~j │ 0000e708: f85f83a8 ldur x8, [x29, #-8]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe708 0xe70c (DW_OP_fbreg -0x8) vcpu_pc(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ kvm_skip_instr:23.18 (adjust_pc.h) Sbepe *vcpu_pc(vcpu) ║+= 4;
~ │ 0000e70c: f9413109 ldr x9, [x8, #608]
~ │ 0000e710: 91001129 add x9, x9, #0x4
~ │ 0000e714: f9013109 str x9, [x8, #608]
│ kvm_skip_instr:24.14 (adjust_pc.h) Sbepe *vcpu_cpsr(║vcpu) &= ~PSR_BTYPE_MASK;
~ │ 0000e718: f94003e8 ldr x8, [sp]
~ │ 0000e71c: f81f03a8 stur x8, [x29, #-16]
k: 0xe720 0xe724 vcpu_cpsr inlined from kvm_skip_instr:24 (adjust_pc.h) <a9465>:
k │ vcpu_cpsr:137.27 (kvm_emulate.h) Sbepe return (unsigned long *)&║vcpu_gp_regs(vcpu)->pstate;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe720 0xe724 (DW_OP_fbreg -0x10) vcpu_cpsr(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~k │ 0000e720: f85f03a8 ldur x8, [x29, #-16]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe720 0xe724 (DW_OP_fbreg -0x10) vcpu_cpsr(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ kvm_skip_instr:24.20 (adjust_pc.h) Sbepe *vcpu_cpsr(vcpu) ║&= ~PSR_BTYPE_MASK;
~ │ 0000e724: f9413509 ldr x9, [x8, #616]
~ │ 0000e728: 9274f529 and x9, x9, #0xfffffffffffff3ff
~ │ 0000e72c: f9013509 str x9, [x8, #616]
~ │ ┌─0000e730: 14000001 b e734 <kvm_skip_instr+0x70>
│ │
│ │ kvm_skip_instr:28.13 (adjust_pc.h) Sbepe *vcpu_cpsr(║vcpu) &= ~DBG_SPSR_SS;
~ └>└>0000e734: f94003e8 ldr x8, [sp] <- 0000e6fc(b)<kvm_skip_instr+0x70>,0000e730(b)<kvm_skip_instr+0x70>
~ 0000e738: f9000fe8 str x8, [sp, #24]
l: 0xe73c 0xe740 vcpu_cpsr inlined from kvm_skip_instr:28 (adjust_pc.h) <a9482>:
l vcpu_cpsr:137.27 (kvm_emulate.h) Sbepe return (unsigned long *)&║vcpu_gp_regs(vcpu)->pstate;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe73c 0xe740 (DW_OP_breg31 0x18) vcpu_cpsr(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~l 0000e73c: f9400fe8 ldr x8, [sp, #24]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe73c 0xe740 (DW_OP_breg31 0x18) vcpu_cpsr(inlined):kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
kvm_skip_instr:28.19 (adjust_pc.h) Sbepe *vcpu_cpsr(vcpu) ║&= ~DBG_SPSR_SS;
~ 0000e740: f9413509 ldr x9, [x8, #616]
~ 0000e744: 926af929 and x9, x9, #0xffffffffffdfffff
~ 0000e748: f9013509 str x9, [x8, #616]
kvm_skip_instr:29.1 (adjust_pc.h) Sbepe ║}
~ 0000e74c: a9437bfd ldp x29, x30, [sp, #48]
~ 0000e750: 910103ff add sp, sp, #0x40
0000e6d0 CFA:r29+16 r29:c-16 r30:c-8
~ 0000e754: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe6c4 0xe758 (DW_OP_breg31 0x0) kvm_skip_instr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:18
**0000e758 <__vgic_v3_get_group>:
+ __vgic_v3_get_group params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe758 0xe798 (DW_OP_fbreg 0x10)
__vgic_v3_get_group:430.0 (vgic-v3-sr.c) Sbepe ║{
0000e758 CFA:r31
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe758 0xe798 (DW_OP_fbreg 0x10) __vgic_v3_get_group:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:429
+esr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe758 0xe798 (DW_OP_fbreg 0xc) __vgic_v3_get_group:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:431
+crm var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe758 0xe798 (DW_OP_fbreg 0x8) __vgic_v3_get_group:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:432
~ 0000e758: d10083ff sub sp, sp, #0x20 <- 0000d840(bl)<__vgic_v3_get_group>,0000da44(bl)<__vgic_v3_get_group>,0000df4c(bl)<__vgic_v3_get_group>,0000ef5c(bl)<__vgic_v3_get_group>,0000f048(bl)<__vgic_v3_get_group>
~ 0000e75c: f9000be0 str x0, [sp, #16]
__vgic_v3_get_group:431.29 (vgic-v3-sr.c) SbePe u32 esr = kvm_vcpu_get_esr(║vcpu);
~ 0000e760: f9400be8 ldr x8, [sp, #16]
~ 0000e764: f9000fe8 str x8, [sp, #24]
m: 0xe768 0xe770 kvm_vcpu_get_esr inlined from __vgic_v3_get_group:431 (vgic-v3-sr.c) <a94e7>:
m kvm_vcpu_get_esr:224.9 (kvm_emulate.h) Sbepe return ║vcpu->arch.fault.esr_el2;
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe768 0xe770 (DW_OP_fbreg 0x18) kvm_vcpu_get_esr(inlined):__vgic_v3_get_group:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~m 0000e768: f9400fe8 ldr x8, [sp, #24]
m kvm_vcpu_get_esr:224.26 (kvm_emulate.h) sbepe return vcpu->arch.fault.║esr_el2;
~m 0000e76c: b9488909 ldr w9, [x8, #2184]
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xe768 0xe770 (DW_OP_fbreg 0x18) kvm_vcpu_get_esr(inlined):__vgic_v3_get_group:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
__vgic_v3_get_group:431.6 (vgic-v3-sr.c) Sbepe u32 ║esr = kvm_vcpu_get_esr(vcpu);
~ 0000e770: b9000fe9 str w9, [sp, #12]
__vgic_v3_get_group:432.12 (vgic-v3-sr.c) Sbepe u8 crm = (║esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
~ 0000e774: b9400fe9 ldr w9, [sp, #12]
__vgic_v3_get_group:432.16 (vgic-v3-sr.c) sbepe u8 crm = (esr ║& ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
~ 0000e778: 53011129 ubfx w9, w9, #1, #4
__vgic_v3_get_group:432.46 (vgic-v3-sr.c) sbepe u8 crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) ║>> ESR_ELx_SYS64_ISS_CRM_SHIFT;
~ 0000e77c: 2a0903e0 mov w0, w9
__vgic_v3_get_group:432.5 (vgic-v3-sr.c) sbepe u8 ║crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
~ 0000e780: 390023e0 strb w0, [sp, #8]
__vgic_v3_get_group:434.9 (vgic-v3-sr.c) Sbepe return ║crm != 8;
~ 0000e784: 394023e9 ldrb w9, [sp, #8]
__vgic_v3_get_group:434.13 (vgic-v3-sr.c) sbepe return crm ║!= 8;
~ 0000e788: 71002129 subs w9, w9, #0x8
~ 0000e78c: 1a9f07e0 cset w0, ne // ne = any
__vgic_v3_get_group:434.2 (vgic-v3-sr.c) sbepe ║return crm != 8;
~ 0000e790: 910083ff add sp, sp, #0x20
0000e75c CFA:r31+32
~ 0000e794: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe758 0xe798 (DW_OP_fbreg 0x10) __vgic_v3_get_group:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:429
-esr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe758 0xe798 (DW_OP_fbreg 0xc) __vgic_v3_get_group:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:431
-crm var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe758 0xe798 (DW_OP_fbreg 0x8) __vgic_v3_get_group:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:432
**0000e798 <__vgic_v3_highest_priority_lr>:
+ __vgic_v3_highest_priority_lr params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe798 0xe8d0 (DW_OP_fbreg -0x8)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe798 0xe8d0 (DW_OP_fbreg -0xc)
+lr_val param pointer(typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8)))) 0xe798 0xe8d0 (DW_OP_fbreg -0x18)
__vgic_v3_highest_priority_lr:441.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe798 0xe8d0 (DW_OP_fbreg -0x8) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:439
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe798 0xe8d0 (DW_OP_fbreg -0xc) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:439
+lr_val param pointer(typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8)))) 0xe798 0xe8d0 (DW_OP_fbreg -0x18) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:440
+used_lrs var unsigned int (base type, DW_ATE_unsigned size:4) 0xe798 0xe8d0 (DW_OP_fbreg -0x1c) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:442
+priority var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe798 0xe8d0 (DW_OP_breg31 0x20) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:443
+i var int (base type, DW_ATE_signed size:4) 0xe798 0xe8d0 (DW_OP_breg31 0x1c) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:444
+lr var int (base type, DW_ATE_signed size:4) 0xe798 0xe8d0 (DW_OP_breg31 0x18) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:444
~ 0000e798: d10143ff sub sp, sp, #0x50 <- 0000d854(bl)<__vgic_v3_highest_priority_lr>,0000df60(bl)<__vgic_v3_highest_priority_lr>
~ 0000e79c: a9047bfd stp x29, x30, [sp, #64]
0000e798 CFA:r31 r29:u r30:u
~ 0000e7a0: 910103fd add x29, sp, #0x40
~ 0000e7a4: f81f83a0 stur x0, [x29, #-8]
~ 0000e7a8: b81f43a1 stur w1, [x29, #-12]
~ 0000e7ac: f81e83a2 stur x2, [x29, #-24]
__vgic_v3_highest_priority_lr:442.26 (vgic-v3-sr.c) SbePe unsigned int used_lrs = ║vcpu->arch.vgic_cpu.vgic_v3.used_lrs;
~ 0000e7b0: f85f83a8 ldur x8, [x29, #-8]
__vgic_v3_highest_priority_lr:442.54 (vgic-v3-sr.c) sbepe unsigned int used_lrs = vcpu->arch.vgic_cpu.vgic_v3.║used_lrs;
~ 0000e7b4: b9500909 ldr w9, [x8, #4104]
__vgic_v3_highest_priority_lr:442.15 (vgic-v3-sr.c) sbepe unsigned int ║used_lrs = vcpu->arch.vgic_cpu.vgic_v3.used_lrs;
~ 0000e7b8: b81e43a9 stur w9, [x29, #-28]
~ 0000e7bc: 52801fe9 mov w9, #0xff // #255
__vgic_v3_highest_priority_lr:443.5 (vgic-v3-sr.c) Sbepe u8 ║priority = GICv3_IDLE_PRIORITY;
~ 0000e7c0: 390083e9 strb w9, [sp, #32]
~ 0000e7c4: 12800009 mov w9, #0xffffffff // #-1
__vgic_v3_highest_priority_lr:444.9 (vgic-v3-sr.c) Sbepe int i, ║lr = -1;
~ 0000e7c8: b9001be9 str w9, [sp, #24]
~ 0000e7cc: 2a1f03e9 mov w9, wzr
__vgic_v3_highest_priority_lr:446.9 (vgic-v3-sr.c) Sbepe for (i ║= 0; i < used_lrs; i++) {
~ 0000e7d0: b9001fe9 str w9, [sp, #28]
__vgic_v3_highest_priority_lr:446.7 (vgic-v3-sr.c) sbepe for (║i = 0; i < used_lrs; i++) {
~ ┌─0000e7d4: 14000001 b e7d8 <__vgic_v3_highest_priority_lr+0x40>
│
│ __vgic_v3_highest_priority_lr:446.14 (vgic-v3-sr.c) sbepe for (i = 0; ║i < used_lrs; i++) {
~ ╔════════>└>0000e7d8: b9401fe8 ldr w8, [sp, #28] <- 0000e7d4(b)<__vgic_v3_highest_priority_lr+0x40>,v0000e898(b)<__vgic_v3_highest_priority_lr+0x40>
║ __vgic_v3_highest_priority_lr:446.18 (vgic-v3-sr.c) sbepe for (i = 0; i < ║used_lrs; i++) {
~ ║ 0000e7dc: b85e43a9 ldur w9, [x29, #-28]
║ __vgic_v3_highest_priority_lr:446.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i < used_lrs; i++) {
~ ║ 0000e7e0: 6b090108 subs w8, w8, w9
~ ║┌──────────0000e7e4: 540005c2 b.cs e89c <__vgic_v3_highest_priority_lr+0x104> // b.hs, b.nlast
║│
~ ║│ ┌─0000e7e8: 14000001 b e7ec <__vgic_v3_highest_priority_lr+0x54> <- 0000e7e4(b.cc-succ)<fallthrough>
║│ │
║│ │ __vgic_v3_highest_priority_lr:447.29 (vgic-v3-sr.c) Sbepe u64 val = __gic_v3_get_lr(║i);
+val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe7ec 0xe88c (DW_OP_breg31 0x10) lexblock:__vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:447
+lr_prio var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe7ec 0xe88c (DW_OP_breg31 0xc) lexblock:__vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:448
~ ║│ └>0000e7ec: b9401fe0 ldr w0, [sp, #28] <- 0000e7e8(b)<__vgic_v3_highest_priority_lr+0x54>
║│ __vgic_v3_highest_priority_lr:447.13 (vgic-v3-sr.c) sbepe u64 val = ║__gic_v3_get_lr(i);
~ ║│ 0000e7f0: 97fff6f0 bl c3b0 <__gic_v3_get_lr>
║│
║│ __vgic_v3_highest_priority_lr:447.7 (vgic-v3-sr.c) sbepe u64 ║val = __gic_v3_get_lr(i);
~ ║│ 0000e7f4: f9000be0 str x0, [sp, #16] <- 0000e7f0(bl-succ)<return>
║│ __vgic_v3_highest_priority_lr:448.17 (vgic-v3-sr.c) Sbepe u8 lr_prio = (║val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
~ ║│ 0000e7f8: 79402fe8 ldrh w8, [sp, #22]
~ ║│ 0000e7fc: 2a0803e0 mov w0, w8
║│ __vgic_v3_highest_priority_lr:448.6 (vgic-v3-sr.c) sbepe u8 ║lr_prio = (val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
~ ║│ 0000e800: 390033e0 strb w0, [sp, #12]
║│ __vgic_v3_highest_priority_lr:451.8 (vgic-v3-sr.c) Sbepe if ((║val & ICH_LR_STATE) != ICH_LR_PENDING_BIT)
~ ║│ 0000e804: f9400be9 ldr x9, [sp, #16]
║│ __vgic_v3_highest_priority_lr:451.7 (vgic-v3-sr.c) sbepe if (║(val & ICH_LR_STATE) != ICH_LR_PENDING_BIT)
~ ║│ 0000e808: d37efd29 lsr x9, x9, #62
~ ║│ 0000e80c: f1000529 subs x9, x9, #0x1
~ ║│ ┌──0000e810: 54000060 b.eq e81c <__vgic_v3_highest_priority_lr+0x84> // b.none
║│ │
~ ║│ │┌─0000e814: 14000001 b e818 <__vgic_v3_highest_priority_lr+0x80> <- 0000e810(b.cc-succ)<fallthrough>
║│ ││
║│ ││ __vgic_v3_highest_priority_lr:452.4 (vgic-v3-sr.c) Sbepe ║continue;
~ ║│┌──────┼└>0000e818: 1400001d b e88c <__vgic_v3_highest_priority_lr+0xf4> <- 0000e814(b)<__vgic_v3_highest_priority_lr+0x80>
║││ │
║││ │ __vgic_v3_highest_priority_lr:455.29 (vgic-v3-sr.c) Sbepe if (!(val & ICH_LR_GROUP) ║&& !(vmcr & ICH_VMCR_ENG0_MASK))
~ ║││ └─>0000e81c: 39405fe8 ldrb w8, [sp, #23] <- 0000e810(b.cc)<__vgic_v3_highest_priority_lr+0x84>
~ ║││ ┌────0000e820: 372000c8 tbnz w8, #4, e838 <__vgic_v3_highest_priority_lr+0xa0>
║││ │
~ ║││ │ ┌─0000e824: 14000001 b e828 <__vgic_v3_highest_priority_lr+0x90> <- 0000e820(b.cc-succ)<fallthrough>
║││ │ │
║││ │ │ __vgic_v3_highest_priority_lr:455.7 (vgic-v3-sr.c) sbepe if (║!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK))
~ ║││ │ └>0000e828: 385f43a8 ldurb w8, [x29, #-12] <- 0000e824(b)<__vgic_v3_highest_priority_lr+0x90>
~ ║││ │ ┌──0000e82c: 37000068 tbnz w8, #0, e838 <__vgic_v3_highest_priority_lr+0xa0>
║││ │ │
~ ║││ │ │┌─0000e830: 14000001 b e834 <__vgic_v3_highest_priority_lr+0x9c> <- 0000e82c(b.cc-succ)<fallthrough>
║││ │ ││
║││ │ ││ __vgic_v3_highest_priority_lr:456.4 (vgic-v3-sr.c) Sbepe ║continue;
~ ║││ ┌──┼─┼└>0000e834: 14000016 b e88c <__vgic_v3_highest_priority_lr+0xf4> <- 0000e830(b)<__vgic_v3_highest_priority_lr+0x9c>
║││ │ │ │
║││ │ │ │ __vgic_v3_highest_priority_lr:459.28 (vgic-v3-sr.c) Sbepe if ((val & ICH_LR_GROUP) ║&& !(vmcr & ICH_VMCR_ENG1_MASK))
~ ║││ │ └>└─>0000e838: 39405fe8 ldrb w8, [sp, #23] <- 0000e820(b.cc)<__vgic_v3_highest_priority_lr+0xa0>,0000e82c(b.cc)<__vgic_v3_highest_priority_lr+0xa0>
~ ║││ │ ┌────0000e83c: 362000c8 tbz w8, #4, e854 <__vgic_v3_highest_priority_lr+0xbc>
║││ │ │
~ ║││ │ │ ┌─0000e840: 14000001 b e844 <__vgic_v3_highest_priority_lr+0xac> <- 0000e83c(b.cc-succ)<fallthrough>
║││ │ │ │
║││ │ │ │ __vgic_v3_highest_priority_lr:459.7 (vgic-v3-sr.c) sbepe if (║(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK))
~ ║││ │ │ └>0000e844: 385f43a8 ldurb w8, [x29, #-12] <- 0000e840(b)<__vgic_v3_highest_priority_lr+0xac>
~ ║││ │ │ ┌──0000e848: 37080068 tbnz w8, #1, e854 <__vgic_v3_highest_priority_lr+0xbc>
║││ │ │ │
~ ║││ │ │ │┌─0000e84c: 14000001 b e850 <__vgic_v3_highest_priority_lr+0xb8> <- 0000e848(b.cc-succ)<fallthrough>
║││ │ │ ││
║││ │ │ ││ __vgic_v3_highest_priority_lr:460.4 (vgic-v3-sr.c) Sbepe ║continue;
~ ║││ │ ┌┼─┼└>0000e850: 1400000f b e88c <__vgic_v3_highest_priority_lr+0xf4> <- 0000e84c(b)<__vgic_v3_highest_priority_lr+0xb8>
║││ │ ││ │
║││ │ ││ │ __vgic_v3_highest_priority_lr:463.7 (vgic-v3-sr.c) Sbepe if (║lr_prio >= priority)
~ ║││ │ │└>└─>0000e854: 394033e8 ldrb w8, [sp, #12] <- 0000e83c(b.cc)<__vgic_v3_highest_priority_lr+0xbc>,0000e848(b.cc)<__vgic_v3_highest_priority_lr+0xbc>
║││ │ │ __vgic_v3_highest_priority_lr:463.18 (vgic-v3-sr.c) sbepe if (lr_prio >= ║priority)
~ ║││ │ │ 0000e858: 394083e9 ldrb w9, [sp, #32]
║││ │ │ __vgic_v3_highest_priority_lr:463.7 (vgic-v3-sr.c) sbepe if (║lr_prio >= priority)
~ ║││ │ │ 0000e85c: 6b090108 subs w8, w8, w9
~ ║││ │ │ ┌──0000e860: 5400006b b.lt e86c <__vgic_v3_highest_priority_lr+0xd4> // b.tstop
║││ │ │ │
~ ║││ │ │ │┌─0000e864: 14000001 b e868 <__vgic_v3_highest_priority_lr+0xd0> <- 0000e860(b.cc-succ)<fallthrough>
║││ │ │ ││
║││ │ │ ││ __vgic_v3_highest_priority_lr:464.4 (vgic-v3-sr.c) Sbepe ║continue;
~ ║││ │ │ ┌┼└>0000e868: 14000009 b e88c <__vgic_v3_highest_priority_lr+0xf4> <- 0000e864(b)<__vgic_v3_highest_priority_lr+0xd0>
║││ │ │ ││
║││ │ │ ││ __vgic_v3_highest_priority_lr:467.14 (vgic-v3-sr.c) Sbepe priority = ║lr_prio;
~ ║││ │ │ │└─>0000e86c: 394033e8 ldrb w8, [sp, #12] <- 0000e860(b.cc)<__vgic_v3_highest_priority_lr+0xd4>
║││ │ │ │ __vgic_v3_highest_priority_lr:467.12 (vgic-v3-sr.c) sbepe priority ║= lr_prio;
~ ║││ │ │ │ 0000e870: 390083e8 strb w8, [sp, #32]
║││ │ │ │ __vgic_v3_highest_priority_lr:468.13 (vgic-v3-sr.c) Sbepe *lr_val = ║val;
~ ║││ │ │ │ 0000e874: f9400be9 ldr x9, [sp, #16]
║││ │ │ │ __vgic_v3_highest_priority_lr:468.4 (vgic-v3-sr.c) sbepe *║lr_val = val;
~ ║││ │ │ │ 0000e878: f85e83aa ldur x10, [x29, #-24]
║││ │ │ │ __vgic_v3_highest_priority_lr:468.11 (vgic-v3-sr.c) sbepe *lr_val ║= val;
~ ║││ │ │ │ 0000e87c: f9000149 str x9, [x10]
║││ │ │ │ __vgic_v3_highest_priority_lr:469.8 (vgic-v3-sr.c) Sbepe lr = i;
~ ║││ │ │ │ 0000e880: b9401fe8 ldr w8, [sp, #28]
║││ │ │ │ __vgic_v3_highest_priority_lr:469.6 (vgic-v3-sr.c) sbepe lr ║= i;
~ ║││ │ │ │ 0000e884: b9001be8 str w8, [sp, #24]
║││ │ │ │ __vgic_v3_highest_priority_lr:470.2 (vgic-v3-sr.c) Sbepe }
~ ║││ │ │ │ ┌─0000e888: 14000001 b e88c <__vgic_v3_highest_priority_lr+0xf4>
-val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe7ec 0xe88c (DW_OP_breg31 0x10) lexblock:__vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:447
-lr_prio var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe7ec 0xe88c (DW_OP_breg31 0xc) lexblock:__vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:448
║││ │ │ │ │
║││ │ │ │ │ __vgic_v3_highest_priority_lr:446.29 (vgic-v3-sr.c) Sbepe for (i = 0; i < used_lrs; i║++) {
~ ║│└>└>└>└>└>0000e88c: b9401fe8 ldr w8, [sp, #28] <- 0000e818(b)<__vgic_v3_highest_priority_lr+0xf4>,0000e834(b)<__vgic_v3_highest_priority_lr+0xf4>,0000e850(b)<__vgic_v3_highest_priority_lr+0xf4>,0000e868(b)<__vgic_v3_highest_priority_lr+0xf4>,0000e888(b)<__vgic_v3_highest_priority_lr+0xf4>
~ ║│ 0000e890: 11000508 add w8, w8, #0x1
~ ║│ 0000e894: b9001fe8 str w8, [sp, #28]
║│ __vgic_v3_highest_priority_lr:446.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i < used_lrs; i++) {
~ ╚╪══════════0000e898: 17ffffd0 b e7d8 <__vgic_v3_highest_priority_lr+0x40>
│
│ __vgic_v3_highest_priority_lr:472.6 (vgic-v3-sr.c) Sbepe if (║lr == -1)
~ └─────────>0000e89c: b9401be8 ldr w8, [sp, #24] <- 0000e7e4(b.cc)<__vgic_v3_highest_priority_lr+0x104>
__vgic_v3_highest_priority_lr:472.6 (vgic-v3-sr.c) sbepe if (║lr == -1)
~ 0000e8a0: 31000508 adds w8, w8, #0x1
~ ┌───0000e8a4: 540000e1 b.ne e8c0 <__vgic_v3_highest_priority_lr+0x128> // b.any
│
~ │ ┌─0000e8a8: 14000001 b e8ac <__vgic_v3_highest_priority_lr+0x114> <- 0000e8a4(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_highest_priority_lr:473.4 (vgic-v3-sr.c) Sbepe *║lr_val = ICC_IAR1_EL1_SPURIOUS;
~ │ └>0000e8ac: f85e83a8 ldur x8, [x29, #-24] <- 0000e8a8(b)<__vgic_v3_highest_priority_lr+0x114>
~ │ 0000e8b0: 52807fe9 mov w9, #0x3ff // #1023
~ │ 0000e8b4: 2a0903ea mov w10, w9
│ __vgic_v3_highest_priority_lr:473.11 (vgic-v3-sr.c) sbepe *lr_val ║= ICC_IAR1_EL1_SPURIOUS;
~ │ 0000e8b8: f900010a str x10, [x8]
│ __vgic_v3_highest_priority_lr:473.3 (vgic-v3-sr.c) sbepe ║*lr_val = ICC_IAR1_EL1_SPURIOUS;
~ │ ┌─0000e8bc: 14000001 b e8c0 <__vgic_v3_highest_priority_lr+0x128>
│ │
│ │ __vgic_v3_highest_priority_lr:475.9 (vgic-v3-sr.c) Sbepe return ║lr;
~ └>└>0000e8c0: b9401be0 ldr w0, [sp, #24] <- 0000e8a4(b.cc)<__vgic_v3_highest_priority_lr+0x128>,0000e8bc(b)<__vgic_v3_highest_priority_lr+0x128>
__vgic_v3_highest_priority_lr:475.2 (vgic-v3-sr.c) sbepe ║return lr;
~ 0000e8c4: a9447bfd ldp x29, x30, [sp, #64]
~ 0000e8c8: 910143ff add sp, sp, #0x50
0000e7a4 CFA:r29+16 r29:c-16 r30:c-8
~ 0000e8cc: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xe798 0xe8d0 (DW_OP_fbreg -0x8) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:439
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe798 0xe8d0 (DW_OP_fbreg -0xc) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:439
-lr_val param pointer(typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8)))) 0xe798 0xe8d0 (DW_OP_fbreg -0x18) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:440
-used_lrs var unsigned int (base type, DW_ATE_unsigned size:4) 0xe798 0xe8d0 (DW_OP_fbreg -0x1c) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:442
-priority var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe798 0xe8d0 (DW_OP_breg31 0x20) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:443
-i var int (base type, DW_ATE_signed size:4) 0xe798 0xe8d0 (DW_OP_breg31 0x1c) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:444
-lr var int (base type, DW_ATE_signed size:4) 0xe798 0xe8d0 (DW_OP_breg31 0x18) __vgic_v3_highest_priority_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:444
**0000e8d0 <__vgic_v3_get_highest_active_priority>:
+ __vgic_v3_get_highest_active_priority params: none
__vgic_v3_get_highest_active_priority:499.0 (vgic-v3-sr.c) Sbepe ║{
+nr_apr_regs var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe8d0 0xe9d0 (DW_OP_fbreg -0x10) __vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:500
+hap var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe8d0 0xe9d0 (DW_OP_breg31 0x1c) __vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:501
+i var int (base type, DW_ATE_signed size:4) 0xe8d0 0xe9d0 (DW_OP_breg31 0x18) __vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:502
~ 0000e8d0: d10143ff sub sp, sp, #0x50 <- 0000d8b8(bl)<__vgic_v3_get_highest_active_priority>,0000e368(bl)<__vgic_v3_get_highest_active_priority>
~ 0000e8d4: a9047bfd stp x29, x30, [sp, #64]
0000e8d0 CFA:r31 r29:u r30:u
~ 0000e8d8: 910103fd add x29, sp, #0x40
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe8dc 0xe8f0 (DW_OP_fbreg -0x18) lexblock:__vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:500
~ 0000e8dc: d53ccb28 mrs x8, s3_4_c12_c11_1
__vgic_v3_get_highest_active_priority:500.19 (vgic-v3-sr.c) SbePe u8 nr_apr_regs = ║vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
~ 0000e8e0: f81e83a8 stur x8, [x29, #-24]
~ 0000e8e4: f85e83a8 ldur x8, [x29, #-24]
~ 0000e8e8: f90013e8 str x8, [sp, #32]
~ 0000e8ec: b94023e9 ldr w9, [sp, #32]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xe8dc 0xe8f0 (DW_OP_fbreg -0x18) lexblock:__vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:500
__vgic_v3_get_highest_active_priority:500.19 (vgic-v3-sr.c) sbepe u8 nr_apr_regs = ║vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
~ 0000e8f0: 531a7129 ubfx w9, w9, #26, #3
~ 0000e8f4: 71001129 subs w9, w9, #0x4
~ 0000e8f8: 5280002a mov w10, #0x1 // #1
~ 0000e8fc: 1ac92149 lsl w9, w10, w9
__vgic_v3_get_highest_active_priority:500.5 (vgic-v3-sr.c) sbepe u8 ║nr_apr_regs = vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
~ 0000e900: 381f03a9 sturb w9, [x29, #-16]
~ 0000e904: 2a1f03e9 mov w9, wzr
__vgic_v3_get_highest_active_priority:501.6 (vgic-v3-sr.c) Sbepe u32 ║hap = 0;
~ 0000e908: b9001fe9 str w9, [sp, #28]
__vgic_v3_get_highest_active_priority:504.9 (vgic-v3-sr.c) Sbepe for (i ║= 0; i < nr_apr_regs; i++) {
~ 0000e90c: b9001be9 str w9, [sp, #24]
__vgic_v3_get_highest_active_priority:504.7 (vgic-v3-sr.c) sbepe for (║i = 0; i < nr_apr_regs; i++) {
~ ┌─0000e910: 14000001 b e914 <__vgic_v3_get_highest_active_priority+0x44>
│
│ __vgic_v3_get_highest_active_priority:504.14 (vgic-v3-sr.c) sbepe for (i = 0; ║i < nr_apr_regs; i++) {
~ ╔══>└>0000e914: b9401be8 ldr w8, [sp, #24] <- 0000e910(b)<__vgic_v3_get_highest_active_priority+0x44>,v0000e9b0(b)<__vgic_v3_get_highest_active_priority+0x44>
║ __vgic_v3_get_highest_active_priority:504.18 (vgic-v3-sr.c) sbepe for (i = 0; i < ║nr_apr_regs; i++) {
~ ║ 0000e918: 385f03a9 ldurb w9, [x29, #-16]
║ __vgic_v3_get_highest_active_priority:504.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i < nr_apr_regs; i++) {
~ ║ 0000e91c: 6b090108 subs w8, w8, w9
~ ║┌────0000e920: 540004aa b.ge e9b4 <__vgic_v3_get_highest_active_priority+0xe4> // b.tcont
║│
~ ║│ ┌─0000e924: 14000001 b e928 <__vgic_v3_get_highest_active_priority+0x58> <- 0000e920(b.cc-succ)<fallthrough>
║│ │
║│ │ __vgic_v3_get_highest_active_priority:517.31 (vgic-v3-sr.c) Sbepe val = __vgic_v3_read_ap0rn(║i);
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe928 0xe9a4 (DW_OP_breg31 0x14) lexblock:__vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:505
~ ║│ └>0000e928: b9401be0 ldr w0, [sp, #24] <- 0000e924(b)<__vgic_v3_get_highest_active_priority+0x58>
║│ __vgic_v3_get_highest_active_priority:517.10 (vgic-v3-sr.c) sbepe val = ║__vgic_v3_read_ap0rn(i);
~ ║│ 0000e92c: 97fff8b7 bl cc08 <__vgic_v3_read_ap0rn>
║│
║│ __vgic_v3_get_highest_active_priority:517.8 (vgic-v3-sr.c) sbepe val ║= __vgic_v3_read_ap0rn(i);
~ ║│ 0000e930: b90017e0 str w0, [sp, #20] <- 0000e92c(bl-succ)<return>
║│ __vgic_v3_get_highest_active_priority:518.31 (vgic-v3-sr.c) Sbepe val |= __vgic_v3_read_ap1rn(║i);
~ ║│ 0000e934: b9401be0 ldr w0, [sp, #24]
║│ __vgic_v3_get_highest_active_priority:518.10 (vgic-v3-sr.c) sbepe val |= ║__vgic_v3_read_ap1rn(i);
~ ║│ 0000e938: 97fff8e2 bl ccc0 <__vgic_v3_read_ap1rn>
║│
║│ __vgic_v3_get_highest_active_priority:518.7 (vgic-v3-sr.c) sbepe val ║|= __vgic_v3_read_ap1rn(i);
~ ║│ 0000e93c: b94017e8 ldr w8, [sp, #20] <- 0000e938(bl-succ)<return>
~ ║│ 0000e940: 2a000108 orr w8, w8, w0
~ ║│ 0000e944: b90017e8 str w8, [sp, #20]
║│ __vgic_v3_get_highest_active_priority:519.8 (vgic-v3-sr.c) Sbepe if (!║val) {
~ ║│ 0000e948: b94017e8 ldr w8, [sp, #20]
║│ __vgic_v3_get_highest_active_priority:519.7 (vgic-v3-sr.c) sbepe if (║!val) {
~ ║│ ┌──0000e94c: 350000c8 cbnz w8, e964 <__vgic_v3_get_highest_active_priority+0x94>
║│ │
~ ║│ │┌─0000e950: 14000001 b e954 <__vgic_v3_get_highest_active_priority+0x84> <- 0000e94c(b.cc-succ)<fallthrough>
║│ ││
║│ ││ __vgic_v3_get_highest_active_priority:520.8 (vgic-v3-sr.c) Sbepe hap ║+= 32;
~ ║│ │└>0000e954: b9401fe8 ldr w8, [sp, #28] <- 0000e950(b)<__vgic_v3_get_highest_active_priority+0x84>
~ ║│ │ 0000e958: 11008108 add w8, w8, #0x20
~ ║│ │ 0000e95c: b9001fe8 str w8, [sp, #28]
║│ │ __vgic_v3_get_highest_active_priority:521.4 (vgic-v3-sr.c) Sbepe ║continue;
~ ║│ │┌─0000e960: 14000011 b e9a4 <__vgic_v3_get_highest_active_priority+0xd4>
║│ ││
║│ ││ __vgic_v3_get_highest_active_priority:524.11 (vgic-v3-sr.c) Sbepe return (║hap + __ffs(val)) << __vgic_v3_bpr_min();
~ ║│ └┼>0000e964: b9401fe8 ldr w8, [sp, #28] <- 0000e94c(b.cc)<__vgic_v3_get_highest_active_priority+0x94>
~ ║│ │ 0000e968: 2a0803e9 mov w9, w8
║│ │ __vgic_v3_get_highest_active_priority:524.23 (vgic-v3-sr.c) sbepe return (hap + __ffs(║val)) << __vgic_v3_bpr_min();
~ ║│ │ 0000e96c: b94017e8 ldr w8, [sp, #20]
~ ║│ │ 0000e970: 2a0803ea mov w10, w8
~ ║│ │ 0000e974: f81f83aa stur x10, [x29, #-8]
n: 0xe978 0xe984 __ffs inlined from __vgic_v3_get_highest_active_priority:524 (vgic-v3-sr.c) <a964e>:<lexical_block>:
n ║│ │ __ffs:13.24 (builtin-__ffs.h) Sbepe return __builtin_ctzl(║word);
+word param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe978 0xe984 (DW_OP_fbreg -0x8) __ffs(inlined):lexblock:__vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~n ║│ │ 0000e978: f85f83aa ldur x10, [x29, #-8]
n ║│ │ __ffs:13.9 (builtin-__ffs.h) sbepe return ║__builtin_ctzl(word);
~n ║│ │ 0000e97c: dac0014a rbit x10, x10
~n ║│ │ 0000e980: dac0114a clz x10, x10
-word param long unsigned int (base type, DW_ATE_unsigned size:8) 0xe978 0xe984 (DW_OP_fbreg -0x8) __ffs(inlined):lexblock:__vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
║│ │ __vgic_v3_get_highest_active_priority:524.15 (vgic-v3-sr.c) Sbepe return (hap ║+ __ffs(val)) << __vgic_v3_bpr_min();
~ ║│ │ 0000e984: 8b0a0129 add x9, x9, x10
~ ║│ │ 0000e988: f90007e9 str x9, [sp, #8]
║│ │ __vgic_v3_get_highest_active_priority:524.32 (vgic-v3-sr.c) sbepe return (hap + __ffs(val)) << ║__vgic_v3_bpr_min();
~ ║│ │ 0000e98c: 9400005d bl eb00 <__vgic_v3_bpr_min>
║│ │
║│ │ __vgic_v3_get_highest_active_priority:524.29 (vgic-v3-sr.c) sbepe return (hap + __ffs(val)) ║<< __vgic_v3_bpr_min();
~ ║│ │ 0000e990: 2a0003e9 mov w9, w0 <- 0000e98c(bl-succ)<return>
~ ║│ │ 0000e994: f94007ea ldr x10, [sp, #8]
~ ║│ │ 0000e998: 9ac92149 lsl x9, x10, x9
║│ │ __vgic_v3_get_highest_active_priority:524.3 (vgic-v3-sr.c) sbepe ║return (hap + __ffs(val)) << __vgic_v3_bpr_min();
~ ║│ │ 0000e99c: b81f43a9 stur w9, [x29, #-12]
~ ║│┌─┼─0000e9a0: 14000008 b e9c0 <__vgic_v3_get_highest_active_priority+0xf0>
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe928 0xe9a4 (DW_OP_breg31 0x14) lexblock:__vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:505
║││ │
║││ │ __vgic_v3_get_highest_active_priority:504.32 (vgic-v3-sr.c) Sbepe for (i = 0; i < nr_apr_regs; i║++) {
~ ║││ └>0000e9a4: b9401be8 ldr w8, [sp, #24] <- 0000e960(b)<__vgic_v3_get_highest_active_priority+0xd4>
~ ║││ 0000e9a8: 11000508 add w8, w8, #0x1
~ ║││ 0000e9ac: b9001be8 str w8, [sp, #24]
║││ __vgic_v3_get_highest_active_priority:504.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i < nr_apr_regs; i++) {
~ ╚╪╪═══0000e9b0: 17ffffd9 b e914 <__vgic_v3_get_highest_active_priority+0x44>
││
~ └┼──>0000e9b4: 52801fe8 mov w8, #0xff // #255 <- 0000e920(b.cc)<__vgic_v3_get_highest_active_priority+0xe4>
│ __vgic_v3_get_highest_active_priority:527.2 (vgic-v3-sr.c) Sbepe ║return GICv3_IDLE_PRIORITY;
~ │ 0000e9b8: b81f43a8 stur w8, [x29, #-12]
~ │ ┌─0000e9bc: 14000001 b e9c0 <__vgic_v3_get_highest_active_priority+0xf0>
│ │
│ │ __vgic_v3_get_highest_active_priority:528.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000e9c0: b85f43a0 ldur w0, [x29, #-12] <- 0000e9a0(b)<__vgic_v3_get_highest_active_priority+0xf0>,0000e9bc(b)<__vgic_v3_get_highest_active_priority+0xf0>
~ 0000e9c4: a9447bfd ldp x29, x30, [sp, #64]
~ 0000e9c8: 910143ff add sp, sp, #0x50
0000e8dc CFA:r29+16 r29:c-16 r30:c-8
~ 0000e9cc: d65f03c0 ret
-nr_apr_regs var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe8d0 0xe9d0 (DW_OP_fbreg -0x10) __vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:500
-hap var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe8d0 0xe9d0 (DW_OP_breg31 0x1c) __vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:501
-i var int (base type, DW_ATE_signed size:4) 0xe8d0 0xe9d0 (DW_OP_breg31 0x18) __vgic_v3_get_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:502
**0000e9d0 <__vgic_v3_pri_to_pre>:
+ __vgic_v3_pri_to_pre params:
+pri param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe9d0 0xea40 (DW_OP_fbreg -0x4)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe9d0 0xea40 (DW_OP_breg31 0x8)
+grp param int (base type, DW_ATE_signed size:4) 0xe9d0 0xea40 (DW_OP_breg31 0x4)
__vgic_v3_pri_to_pre:555.0 (vgic-v3-sr.c) Sbepe ║{
+pri param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe9d0 0xea40 (DW_OP_fbreg -0x4) __vgic_v3_pri_to_pre:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:554
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe9d0 0xea40 (DW_OP_breg31 0x8) __vgic_v3_pri_to_pre:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:554
+grp param int (base type, DW_ATE_signed size:4) 0xe9d0 0xea40 (DW_OP_breg31 0x4) __vgic_v3_pri_to_pre:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:554
+bpr var unsigned int (base type, DW_ATE_unsigned size:4) 0xe9d0 0xea40 (DW_OP_breg31 0x0) __vgic_v3_pri_to_pre:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:556
~ 0000e9d0: d10083ff sub sp, sp, #0x20 <- 0000d8d0(bl)<__vgic_v3_pri_to_pre>,0000dad4(bl)<__vgic_v3_pri_to_pre>,0000ea64(bl)<__vgic_v3_pri_to_pre>
~ 0000e9d4: a9017bfd stp x29, x30, [sp, #16]
0000e9d0 CFA:r31 r29:u r30:u
~ 0000e9d8: 910043fd add x29, sp, #0x10
~ 0000e9dc: 381fc3a0 sturb w0, [x29, #-4]
~ 0000e9e0: b9000be1 str w1, [sp, #8]
~ 0000e9e4: b90007e2 str w2, [sp, #4]
__vgic_v3_pri_to_pre:558.7 (vgic-v3-sr.c) SbePe if (!║grp)
~ 0000e9e8: b94007e8 ldr w8, [sp, #4]
__vgic_v3_pri_to_pre:558.6 (vgic-v3-sr.c) sbepe if (║!grp)
~ ┌──0000e9ec: 350000e8 cbnz w8, ea08 <__vgic_v3_pri_to_pre+0x38>
│
~ │┌─0000e9f0: 14000001 b e9f4 <__vgic_v3_pri_to_pre+0x24> <- 0000e9ec(b.cc-succ)<fallthrough>
││
││ __vgic_v3_pri_to_pre:559.28 (vgic-v3-sr.c) Sbepe bpr = __vgic_v3_get_bpr0(║vmcr) + 1;
~ │└>0000e9f4: b9400be0 ldr w0, [sp, #8] <- 0000e9f0(b)<__vgic_v3_pri_to_pre+0x24>
│ __vgic_v3_pri_to_pre:559.9 (vgic-v3-sr.c) sbepe bpr = ║__vgic_v3_get_bpr0(vmcr) + 1;
~ │ 0000e9f8: 9400004c bl eb28 <__vgic_v3_get_bpr0>
│
│ __vgic_v3_pri_to_pre:559.34 (vgic-v3-sr.c) sbepe bpr = __vgic_v3_get_bpr0(vmcr) ║+ 1;
~ │ 0000e9fc: 11000408 add w8, w0, #0x1 <- 0000e9f8(bl-succ)<return>
│ __vgic_v3_pri_to_pre:559.7 (vgic-v3-sr.c) sbepe bpr ║= __vgic_v3_get_bpr0(vmcr) + 1;
~ │ 0000ea00: b90003e8 str w8, [sp]
│ __vgic_v3_pri_to_pre:559.3 (vgic-v3-sr.c) sbepe ║bpr = __vgic_v3_get_bpr0(vmcr) + 1;
~ ┌┼──0000ea04: 14000005 b ea18 <__vgic_v3_pri_to_pre+0x48>
││
││ __vgic_v3_pri_to_pre:561.28 (vgic-v3-sr.c) Sbepe bpr = __vgic_v3_get_bpr1(║vmcr);
~ │└─>0000ea08: b9400be0 ldr w0, [sp, #8] <- 0000e9ec(b.cc)<__vgic_v3_pri_to_pre+0x38>
│ __vgic_v3_pri_to_pre:561.9 (vgic-v3-sr.c) sbepe bpr = ║__vgic_v3_get_bpr1(vmcr);
~ │ 0000ea0c: 9400004d bl eb40 <__vgic_v3_get_bpr1>
│
│ __vgic_v3_pri_to_pre:561.7 (vgic-v3-sr.c) sbepe bpr ║= __vgic_v3_get_bpr1(vmcr);
~ │ 0000ea10: b90003e0 str w0, [sp] <- 0000ea0c(bl-succ)<return>
~ │ ┌─0000ea14: 14000001 b ea18 <__vgic_v3_pri_to_pre+0x48>
│ │
│ │ __vgic_v3_pri_to_pre:563.9 (vgic-v3-sr.c) Sbepe return ║pri & (GENMASK(7, 0) << bpr);
~ └>└>0000ea18: 385fc3a8 ldurb w8, [x29, #-4] <- 0000ea04(b)<__vgic_v3_pri_to_pre+0x48>,0000ea14(b)<__vgic_v3_pri_to_pre+0x48>
__vgic_v3_pri_to_pre:563.33 (vgic-v3-sr.c) sbepe return pri & (GENMASK(7, 0) << ║bpr);
~ 0000ea1c: b94003e9 ldr w9, [sp]
~ 0000ea20: 2a0903ea mov w10, w9
~ 0000ea24: 52801fe9 mov w9, #0xff // #255
~ 0000ea28: 2a0903eb mov w11, w9
__vgic_v3_pri_to_pre:563.30 (vgic-v3-sr.c) sbepe return pri & (GENMASK(7, 0) ║<< bpr);
~ 0000ea2c: 9aca216a lsl x10, x11, x10
__vgic_v3_pri_to_pre:563.13 (vgic-v3-sr.c) sbepe return pri ║& (GENMASK(7, 0) << bpr);
~ 0000ea30: 0a0a0100 and w0, w8, w10
__vgic_v3_pri_to_pre:563.2 (vgic-v3-sr.c) sbepe ║return pri & (GENMASK(7, 0) << bpr);
~ 0000ea34: a9417bfd ldp x29, x30, [sp, #16]
~ 0000ea38: 910083ff add sp, sp, #0x20
0000e9dc CFA:r29+16 r29:c-16 r30:c-8
~ 0000ea3c: d65f03c0 ret
-pri param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xe9d0 0xea40 (DW_OP_fbreg -0x4) __vgic_v3_pri_to_pre:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:554
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xe9d0 0xea40 (DW_OP_breg31 0x8) __vgic_v3_pri_to_pre:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:554
-grp param int (base type, DW_ATE_signed size:4) 0xe9d0 0xea40 (DW_OP_breg31 0x4) __vgic_v3_pri_to_pre:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:554
-bpr var unsigned int (base type, DW_ATE_unsigned size:4) 0xe9d0 0xea40 (DW_OP_breg31 0x0) __vgic_v3_pri_to_pre:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:556
**0000ea40 <__vgic_v3_set_active_priority>:
+ __vgic_v3_set_active_priority params:
+pri param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xea40 0xeb00 (DW_OP_fbreg -0x4)
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xea40 0xeb00 (DW_OP_fbreg -0x8)
+grp param int (base type, DW_ATE_signed size:4) 0xea40 0xeb00 (DW_OP_fbreg -0xc)
__vgic_v3_set_active_priority:573.0 (vgic-v3-sr.c) Sbepe ║{
+pri param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xea40 0xeb00 (DW_OP_fbreg -0x4) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:572
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xea40 0xeb00 (DW_OP_fbreg -0x8) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:572
+grp param int (base type, DW_ATE_signed size:4) 0xea40 0xeb00 (DW_OP_fbreg -0xc) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:572
+pre var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xea40 0xeb00 (DW_OP_breg31 0x10) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:574
+ap var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xea40 0xeb00 (DW_OP_breg31 0xc) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:574
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xea40 0xeb00 (DW_OP_breg31 0x8) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:575
+apr var int (base type, DW_ATE_signed size:4) 0xea40 0xeb00 (DW_OP_breg31 0x4) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:576
~ 0000ea40: d100c3ff sub sp, sp, #0x30 <- 0000d930(bl)<__vgic_v3_set_active_priority>
~ 0000ea44: a9027bfd stp x29, x30, [sp, #32]
0000ea40 CFA:r31 r29:u r30:u
~ 0000ea48: 910083fd add x29, sp, #0x20
~ 0000ea4c: 381fc3a0 sturb w0, [x29, #-4]
~ 0000ea50: b81f83a1 stur w1, [x29, #-8]
~ 0000ea54: b81f43a2 stur w2, [x29, #-12]
__vgic_v3_set_active_priority:578.34 (vgic-v3-sr.c) SbePe pre = __vgic_v3_pri_to_pre(pri, ║vmcr, grp);
~ 0000ea58: b85f83a1 ldur w1, [x29, #-8]
__vgic_v3_set_active_priority:578.40 (vgic-v3-sr.c) sbepe pre = __vgic_v3_pri_to_pre(pri, vmcr, ║grp);
~ 0000ea5c: b85f43a2 ldur w2, [x29, #-12]
__vgic_v3_set_active_priority:578.8 (vgic-v3-sr.c) sbepe pre = ║__vgic_v3_pri_to_pre(pri, vmcr, grp);
~ 0000ea60: 385fc3a0 ldurb w0, [x29, #-4]
~ 0000ea64: 97ffffdb bl e9d0 <__vgic_v3_pri_to_pre>
__vgic_v3_set_active_priority:578.6 (vgic-v3-sr.c) sbepe pre ║= __vgic_v3_pri_to_pre(pri, vmcr, grp);
~ 0000ea68: 390043e0 strb w0, [sp, #16] <- 0000ea64(bl-succ)<return>
__vgic_v3_set_active_priority:579.7 (vgic-v3-sr.c) Sbepe ap = ║pre >> __vgic_v3_bpr_min();
~ 0000ea6c: 394043e8 ldrb w8, [sp, #16]
~ 0000ea70: b90003e8 str w8, [sp]
__vgic_v3_set_active_priority:579.14 (vgic-v3-sr.c) sbepe ap = pre >> ║__vgic_v3_bpr_min();
~ 0000ea74: 94000023 bl eb00 <__vgic_v3_bpr_min>
~ 0000ea78: b94003e8 ldr w8, [sp] <- 0000ea74(bl-succ)<return>
__vgic_v3_set_active_priority:579.11 (vgic-v3-sr.c) sbepe ap = pre ║>> __vgic_v3_bpr_min();
~ 0000ea7c: 1ac02508 lsr w8, w8, w0
__vgic_v3_set_active_priority:579.5 (vgic-v3-sr.c) sbepe ap ║= pre >> __vgic_v3_bpr_min();
~ 0000ea80: 390033e8 strb w8, [sp, #12]
__vgic_v3_set_active_priority:580.8 (vgic-v3-sr.c) Sbepe apr = ║ap / 32;
~ 0000ea84: 394033e8 ldrb w8, [sp, #12]
__vgic_v3_set_active_priority:580.11 (vgic-v3-sr.c) sbepe apr = ap ║/ 32;
~ 0000ea88: 53057d08 lsr w8, w8, #5
__vgic_v3_set_active_priority:580.6 (vgic-v3-sr.c) sbepe apr ║= ap / 32;
~ 0000ea8c: b90007e8 str w8, [sp, #4]
__vgic_v3_set_active_priority:582.7 (vgic-v3-sr.c) Sbepe if (!║grp) {
~ 0000ea90: b85f43a8 ldur w8, [x29, #-12]
__vgic_v3_set_active_priority:582.6 (vgic-v3-sr.c) sbepe if (║!grp) {
~ ┌──0000ea94: 350001a8 cbnz w8, eac8 <__vgic_v3_set_active_priority+0x88>
│
~ │┌─0000ea98: 14000001 b ea9c <__vgic_v3_set_active_priority+0x5c> <- 0000ea94(b.cc-succ)<fallthrough>
││
││ __vgic_v3_set_active_priority:583.30 (vgic-v3-sr.c) Sbepe val = __vgic_v3_read_ap0rn(║apr);
~ │└>0000ea9c: b94007e0 ldr w0, [sp, #4] <- 0000ea98(b)<__vgic_v3_set_active_priority+0x5c>
│ __vgic_v3_set_active_priority:583.9 (vgic-v3-sr.c) sbepe val = ║__vgic_v3_read_ap0rn(apr);
~ │ 0000eaa0: 97fff85a bl cc08 <__vgic_v3_read_ap0rn>
│
│ __vgic_v3_set_active_priority:583.7 (vgic-v3-sr.c) sbepe val ║= __vgic_v3_read_ap0rn(apr);
~ │ 0000eaa4: b9000be0 str w0, [sp, #8] <- 0000eaa0(bl-succ)<return>
│ __vgic_v3_set_active_priority:584.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap0rn(║val | BIT(ap % 32), apr);
~ │ 0000eaa8: b9400be8 ldr w8, [sp, #8]
│ __vgic_v3_set_active_priority:584.31 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap0rn(val | ║BIT(ap % 32), apr);
~ │ 0000eaac: 394033e9 ldrb w9, [sp, #12]
~ │ 0000eab0: 5280002a mov w10, #0x1 // #1
│ __vgic_v3_set_active_priority:584.29 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap0rn(val ║| BIT(ap % 32), apr);
~ │ 0000eab4: 1ac92149 lsl w9, w10, w9
~ │ 0000eab8: 2a090100 orr w0, w8, w9
│ __vgic_v3_set_active_priority:584.45 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap0rn(val | BIT(ap % 32), ║apr);
~ │ 0000eabc: b94007e1 ldr w1, [sp, #4]
│ __vgic_v3_set_active_priority:584.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap0rn(val | BIT(ap % 32), apr);
~ │ 0000eac0: 97fff8f9 bl cea4 <__vgic_v3_write_ap0rn>
│
│ __vgic_v3_set_active_priority:585.2 (vgic-v3-sr.c) Sbepe ║} else {
~ ┌┼──0000eac4: 1400000c b eaf4 <__vgic_v3_set_active_priority+0xb4> <- 0000eac0(bl-succ)<return>
││
││ __vgic_v3_set_active_priority:586.30 (vgic-v3-sr.c) Sbepe val = __vgic_v3_read_ap1rn(║apr);
~ │└─>0000eac8: b94007e0 ldr w0, [sp, #4] <- 0000ea94(b.cc)<__vgic_v3_set_active_priority+0x88>
│ __vgic_v3_set_active_priority:586.9 (vgic-v3-sr.c) sbepe val = ║__vgic_v3_read_ap1rn(apr);
~ │ 0000eacc: 97fff87d bl ccc0 <__vgic_v3_read_ap1rn>
│
│ __vgic_v3_set_active_priority:586.7 (vgic-v3-sr.c) sbepe val ║= __vgic_v3_read_ap1rn(apr);
~ │ 0000ead0: b9000be0 str w0, [sp, #8] <- 0000eacc(bl-succ)<return>
│ __vgic_v3_set_active_priority:587.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap1rn(║val | BIT(ap % 32), apr);
~ │ 0000ead4: b9400be8 ldr w8, [sp, #8]
│ __vgic_v3_set_active_priority:587.31 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap1rn(val | ║BIT(ap % 32), apr);
~ │ 0000ead8: 394033e9 ldrb w9, [sp, #12]
~ │ 0000eadc: 5280002a mov w10, #0x1 // #1
│ __vgic_v3_set_active_priority:587.29 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap1rn(val ║| BIT(ap % 32), apr);
~ │ 0000eae0: 1ac92149 lsl w9, w10, w9
~ │ 0000eae4: 2a090100 orr w0, w8, w9
│ __vgic_v3_set_active_priority:587.45 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap1rn(val | BIT(ap % 32), ║apr);
~ │ 0000eae8: b94007e1 ldr w1, [sp, #4]
│ __vgic_v3_set_active_priority:587.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap1rn(val | BIT(ap % 32), apr);
~ │ 0000eaec: 97fff91f bl cf68 <__vgic_v3_write_ap1rn>
│
~ │ ┌─0000eaf0: 14000001 b eaf4 <__vgic_v3_set_active_priority+0xb4> <- 0000eaec(bl-succ)<return>
│ │
│ │ __vgic_v3_set_active_priority:589.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000eaf4: a9427bfd ldp x29, x30, [sp, #32] <- 0000eac4(b)<__vgic_v3_set_active_priority+0xb4>,0000eaf0(b)<__vgic_v3_set_active_priority+0xb4>
~ 0000eaf8: 9100c3ff add sp, sp, #0x30
0000ea4c CFA:r29+16 r29:c-16 r30:c-8
~ 0000eafc: d65f03c0 ret
-pri param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xea40 0xeb00 (DW_OP_fbreg -0x4) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:572
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xea40 0xeb00 (DW_OP_fbreg -0x8) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:572
-grp param int (base type, DW_ATE_signed size:4) 0xea40 0xeb00 (DW_OP_fbreg -0xc) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:572
-pre var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xea40 0xeb00 (DW_OP_breg31 0x10) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:574
-ap var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xea40 0xeb00 (DW_OP_breg31 0xc) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:574
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xea40 0xeb00 (DW_OP_breg31 0x8) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:575
-apr var int (base type, DW_ATE_signed size:4) 0xea40 0xeb00 (DW_OP_breg31 0x4) __vgic_v3_set_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:576
**0000eb00 <__vgic_v3_bpr_min>:
+ __vgic_v3_bpr_min params: none
__vgic_v3_bpr_min:424.0 (vgic-v3-sr.c) Sbepe ║{
0000eb00 CFA:r31
~ 0000eb00: d10043ff sub sp, sp, #0x10 <- 0000dd00(bl)<__vgic_v3_bpr_min>,0000e1fc(bl)<__vgic_v3_bpr_min>,0000e98c(bl)<__vgic_v3_bpr_min>,0000ea74(bl)<__vgic_v3_bpr_min>,0000ed70(bl)<__vgic_v3_bpr_min>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xeb04 0xeb1c (DW_OP_fbreg 0x8) lexblock:__vgic_v3_bpr_min:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:426
~ 0000eb04: d53ccb28 mrs x8, s3_4_c12_c11_1
__vgic_v3_bpr_min:426.13 (vgic-v3-sr.c) SbePe return 8 - ║vtr_to_nr_pre_bits(read_gicreg(ICH_VTR_EL2));
~ 0000eb08: f90007e8 str x8, [sp, #8]
~ 0000eb0c: f94007e8 ldr x8, [sp, #8]
~ 0000eb10: f90003e8 str x8, [sp]
~ 0000eb14: b94003e9 ldr w9, [sp]
~ 0000eb18: 528000ea mov w10, #0x7 // #7
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xeb04 0xeb1c (DW_OP_fbreg 0x8) lexblock:__vgic_v3_bpr_min:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:426
__vgic_v3_bpr_min:426.11 (vgic-v3-sr.c) sbepe return 8 ║- vtr_to_nr_pre_bits(read_gicreg(ICH_VTR_EL2));
~ 0000eb1c: 0a696940 bic w0, w10, w9, lsr #26
__vgic_v3_bpr_min:426.2 (vgic-v3-sr.c) sbepe ║return 8 - vtr_to_nr_pre_bits(read_gicreg(ICH_VTR_EL2));
~ 0000eb20: 910043ff add sp, sp, #0x10
0000eb04 CFA:r31+16
~ 0000eb24: d65f03c0 ret
**0000eb28 <__vgic_v3_get_bpr0>:
+ __vgic_v3_get_bpr0 params:
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xeb28 0xeb40 (DW_OP_fbreg 0xc)
__vgic_v3_get_bpr0:531.0 (vgic-v3-sr.c) Sbepe ║{
0000eb28 CFA:r31
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xeb28 0xeb40 (DW_OP_fbreg 0xc) __vgic_v3_get_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:530
~ 0000eb28: d10043ff sub sp, sp, #0x10 <- 0000e13c(bl)<__vgic_v3_get_bpr0>,0000e9f8(bl)<__vgic_v3_get_bpr0>,0000eb60(bl)<__vgic_v3_get_bpr0>
~ 0000eb2c: b9000fe0 str w0, [sp, #12]
__vgic_v3_get_bpr0:532.10 (vgic-v3-sr.c) SbePe return (║vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
~ 0000eb30: b9400fe8 ldr w8, [sp, #12]
__vgic_v3_get_bpr0:532.37 (vgic-v3-sr.c) sbepe return (vmcr & ICH_VMCR_BPR0_MASK) ║>> ICH_VMCR_BPR0_SHIFT;
~ 0000eb34: 53155d00 ubfx w0, w8, #21, #3
__vgic_v3_get_bpr0:532.2 (vgic-v3-sr.c) sbepe ║return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
~ 0000eb38: 910043ff add sp, sp, #0x10
0000eb2c CFA:r31+16
~ 0000eb3c: d65f03c0 ret
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xeb28 0xeb40 (DW_OP_fbreg 0xc) __vgic_v3_get_bpr0:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:530
**0000eb40 <__vgic_v3_get_bpr1>:
+ __vgic_v3_get_bpr1 params:
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xeb40 0xebac (DW_OP_fbreg -0x4)
__vgic_v3_get_bpr1:536.0 (vgic-v3-sr.c) Sbepe ║{
+vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xeb40 0xebac (DW_OP_fbreg -0x4) __vgic_v3_get_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:535
+bpr var unsigned int (base type, DW_ATE_unsigned size:4) 0xeb40 0xebac (DW_OP_breg31 0x8) __vgic_v3_get_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:537
~ 0000eb40: d10083ff sub sp, sp, #0x20 <- 0000dc40(bl)<__vgic_v3_get_bpr1>,0000ea0c(bl)<__vgic_v3_get_bpr1>
~ 0000eb44: a9017bfd stp x29, x30, [sp, #16]
0000eb40 CFA:r31 r29:u r30:u
~ 0000eb48: 910043fd add x29, sp, #0x10
~ 0000eb4c: b81fc3a0 stur w0, [x29, #-4]
__vgic_v3_get_bpr1:539.6 (vgic-v3-sr.c) SbePe if (║vmcr & ICH_VMCR_CBPR_MASK) {
~ 0000eb50: 385fc3a8 ldurb w8, [x29, #-4]
~ ┌──0000eb54: 362001c8 tbz w8, #4, eb8c <__vgic_v3_get_bpr1+0x4c>
│
~ │┌─0000eb58: 14000001 b eb5c <__vgic_v3_get_bpr1+0x1c> <- 0000eb54(b.cc-succ)<fallthrough>
││
││ __vgic_v3_get_bpr1:540.28 (vgic-v3-sr.c) Sbepe bpr = __vgic_v3_get_bpr0(║vmcr);
~ │└>0000eb5c: b85fc3a0 ldur w0, [x29, #-4] <- 0000eb58(b)<__vgic_v3_get_bpr1+0x1c>
│ __vgic_v3_get_bpr1:540.9 (vgic-v3-sr.c) sbepe bpr = ║__vgic_v3_get_bpr0(vmcr);
~ │ 0000eb60: 97fffff2 bl eb28 <__vgic_v3_get_bpr0>
│
│ __vgic_v3_get_bpr1:540.7 (vgic-v3-sr.c) sbepe bpr ║= __vgic_v3_get_bpr0(vmcr);
~ │ 0000eb64: b9000be0 str w0, [sp, #8] <- 0000eb60(bl-succ)<return>
│ __vgic_v3_get_bpr1:541.7 (vgic-v3-sr.c) Sbepe if (║bpr < 7)
~ │ 0000eb68: b9400be8 ldr w8, [sp, #8]
│ __vgic_v3_get_bpr1:541.7 (vgic-v3-sr.c) sbepe if (║bpr < 7)
~ │ 0000eb6c: 71001908 subs w8, w8, #0x6
~ ┌──┼──0000eb70: 540000c8 b.hi eb88 <__vgic_v3_get_bpr1+0x48> // b.pmore
│ │
~ │ │┌─0000eb74: 14000001 b eb78 <__vgic_v3_get_bpr1+0x38> <- 0000eb70(b.cc-succ)<fallthrough>
│ ││
│ ││ __vgic_v3_get_bpr1:542.7 (vgic-v3-sr.c) Sbepe bpr║++;
~ │ │└>0000eb78: b9400be8 ldr w8, [sp, #8] <- 0000eb74(b)<__vgic_v3_get_bpr1+0x38>
~ │ │ 0000eb7c: 11000508 add w8, w8, #0x1
~ │ │ 0000eb80: b9000be8 str w8, [sp, #8]
│ │ __vgic_v3_get_bpr1:542.4 (vgic-v3-sr.c) sbepe ║bpr++;
~ │ │┌─0000eb84: 14000001 b eb88 <__vgic_v3_get_bpr1+0x48>
│ ││
│ ││ __vgic_v3_get_bpr1:543.2 (vgic-v3-sr.c) Sbepe ║} else {
~ └>┌┼└>0000eb88: 14000005 b eb9c <__vgic_v3_get_bpr1+0x5c> <- 0000eb70(b.cc)<__vgic_v3_get_bpr1+0x48>,0000eb84(b)<__vgic_v3_get_bpr1+0x48>
││
││ __vgic_v3_get_bpr1:544.10 (vgic-v3-sr.c) Sbepe bpr = (║vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
~ │└─>0000eb8c: b85fc3a8 ldur w8, [x29, #-4] <- 0000eb54(b.cc)<__vgic_v3_get_bpr1+0x4c>
│ __vgic_v3_get_bpr1:544.37 (vgic-v3-sr.c) sbepe bpr = (vmcr & ICH_VMCR_BPR1_MASK) ║>> ICH_VMCR_BPR1_SHIFT;
~ │ 0000eb90: 53125108 ubfx w8, w8, #18, #3
│ __vgic_v3_get_bpr1:544.7 (vgic-v3-sr.c) sbepe bpr ║= (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
~ │ 0000eb94: b9000be8 str w8, [sp, #8]
~ │ ┌─0000eb98: 14000001 b eb9c <__vgic_v3_get_bpr1+0x5c>
│ │
│ │ __vgic_v3_get_bpr1:547.9 (vgic-v3-sr.c) Sbepe return ║bpr;
~ └>└>0000eb9c: b9400be0 ldr w0, [sp, #8] <- 0000eb88(b)<__vgic_v3_get_bpr1+0x5c>,0000eb98(b)<__vgic_v3_get_bpr1+0x5c>
__vgic_v3_get_bpr1:547.2 (vgic-v3-sr.c) sbepe ║return bpr;
~ 0000eba0: a9417bfd ldp x29, x30, [sp, #16]
~ 0000eba4: 910083ff add sp, sp, #0x20
0000eb4c CFA:r29+16 r29:c-16 r30:c-8
~ 0000eba8: d65f03c0 ret
-vmcr param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xeb40 0xebac (DW_OP_fbreg -0x4) __vgic_v3_get_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:535
-bpr var unsigned int (base type, DW_ATE_unsigned size:4) 0xeb40 0xebac (DW_OP_breg31 0x8) __vgic_v3_get_bpr1:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:537
**0000ebac <__vgic_v3_clear_highest_active_priority>:
+ __vgic_v3_clear_highest_active_priority params: none
__vgic_v3_clear_highest_active_priority:592.0 (vgic-v3-sr.c) Sbepe ║{
+nr_apr_regs var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xebac 0xedb0 (DW_OP_fbreg -0x18) __vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:593
+hap var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xebac 0xedb0 (DW_OP_fbreg -0x2c) __vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:594
+i var int (base type, DW_ATE_signed size:4) 0xebac 0xedb0 (DW_OP_breg31 0x30) __vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:595
~ 0000ebac: d101c3ff sub sp, sp, #0x70 <- 0000da4c(bl)<__vgic_v3_clear_highest_active_priority>
~ 0000ebb0: a9067bfd stp x29, x30, [sp, #96]
0000ebac CFA:r31 r29:u r30:u
~ 0000ebb4: 910183fd add x29, sp, #0x60
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xebb8 0xebcc (DW_OP_fbreg -0x20) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:593
~ 0000ebb8: d53ccb28 mrs x8, s3_4_c12_c11_1
__vgic_v3_clear_highest_active_priority:593.19 (vgic-v3-sr.c) SbePe u8 nr_apr_regs = ║vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
~ 0000ebbc: f81e03a8 stur x8, [x29, #-32]
~ 0000ebc0: f85e03a8 ldur x8, [x29, #-32]
~ 0000ebc4: f81d83a8 stur x8, [x29, #-40]
~ 0000ebc8: b85d83a9 ldur w9, [x29, #-40]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xebb8 0xebcc (DW_OP_fbreg -0x20) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:593
__vgic_v3_clear_highest_active_priority:593.19 (vgic-v3-sr.c) sbepe u8 nr_apr_regs = ║vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
~ 0000ebcc: 531a7129 ubfx w9, w9, #26, #3
~ 0000ebd0: 71001129 subs w9, w9, #0x4
~ 0000ebd4: 5280002a mov w10, #0x1 // #1
~ 0000ebd8: 1ac92149 lsl w9, w10, w9
__vgic_v3_clear_highest_active_priority:593.5 (vgic-v3-sr.c) sbepe u8 ║nr_apr_regs = vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
~ 0000ebdc: 381e83a9 sturb w9, [x29, #-24]
~ 0000ebe0: 2a1f03e9 mov w9, wzr
__vgic_v3_clear_highest_active_priority:594.6 (vgic-v3-sr.c) Sbepe u32 ║hap = 0;
~ 0000ebe4: b81d43a9 stur w9, [x29, #-44]
__vgic_v3_clear_highest_active_priority:597.9 (vgic-v3-sr.c) Sbepe for (i ║= 0; i < nr_apr_regs; i++) {
~ 0000ebe8: b90033e9 str w9, [sp, #48]
__vgic_v3_clear_highest_active_priority:597.7 (vgic-v3-sr.c) sbepe for (║i = 0; i < nr_apr_regs; i++) {
~ ┌─0000ebec: 14000001 b ebf0 <__vgic_v3_clear_highest_active_priority+0x44>
│
│ __vgic_v3_clear_highest_active_priority:597.14 (vgic-v3-sr.c) sbepe for (i = 0; ║i < nr_apr_regs; i++) {
~ ╔════>└>0000ebf0: b94033e8 ldr w8, [sp, #48] <- 0000ebec(b)<__vgic_v3_clear_highest_active_priority+0x44>,v0000ed90(b)<__vgic_v3_clear_highest_active_priority+0x44>
║ __vgic_v3_clear_highest_active_priority:597.18 (vgic-v3-sr.c) sbepe for (i = 0; i < ║nr_apr_regs; i++) {
~ ║ 0000ebf4: 385e83a9 ldurb w9, [x29, #-24]
║ __vgic_v3_clear_highest_active_priority:597.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i < nr_apr_regs; i++) {
~ ║ 0000ebf8: 6b090108 subs w8, w8, w9
~ ║┌──────0000ebfc: 54000cca b.ge ed94 <__vgic_v3_clear_highest_active_priority+0x1e8> // b.tcont
║│
~ ║│ ┌─0000ec00: 14000001 b ec04 <__vgic_v3_clear_highest_active_priority+0x58> <- 0000ebfc(b.cc-succ)<fallthrough>
║│ │
║│ │ __vgic_v3_clear_highest_active_priority:601.30 (vgic-v3-sr.c) Sbepe ap0 = __vgic_v3_read_ap0rn(║i);
+ap0 var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xec04 0xed84 (DW_OP_breg31 0x2c) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:598
+ap1 var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xec04 0xed84 (DW_OP_breg31 0x28) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:598
+c0 var int (base type, DW_ATE_signed size:4) 0xec04 0xed84 (DW_OP_breg31 0x24) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:599
+c1 var int (base type, DW_ATE_signed size:4) 0xec04 0xed84 (DW_OP_breg31 0x20) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:599
~ ║│ └>0000ec04: b94033e0 ldr w0, [sp, #48] <- 0000ec00(b)<__vgic_v3_clear_highest_active_priority+0x58>
║│ __vgic_v3_clear_highest_active_priority:601.9 (vgic-v3-sr.c) sbepe ap0 = ║__vgic_v3_read_ap0rn(i);
~ ║│ 0000ec08: 97fff800 bl cc08 <__vgic_v3_read_ap0rn>
║│
║│ __vgic_v3_clear_highest_active_priority:601.7 (vgic-v3-sr.c) sbepe ap0 ║= __vgic_v3_read_ap0rn(i);
~ ║│ 0000ec0c: b9002fe0 str w0, [sp, #44] <- 0000ec08(bl-succ)<return>
║│ __vgic_v3_clear_highest_active_priority:602.30 (vgic-v3-sr.c) Sbepe ap1 = __vgic_v3_read_ap1rn(║i);
~ ║│ 0000ec10: b94033e0 ldr w0, [sp, #48]
║│ __vgic_v3_clear_highest_active_priority:602.9 (vgic-v3-sr.c) sbepe ap1 = ║__vgic_v3_read_ap1rn(i);
~ ║│ 0000ec14: 97fff82b bl ccc0 <__vgic_v3_read_ap1rn>
║│
║│ __vgic_v3_clear_highest_active_priority:602.7 (vgic-v3-sr.c) sbepe ap1 ║= __vgic_v3_read_ap1rn(i);
~ ║│ 0000ec18: b9002be0 str w0, [sp, #40] <- 0000ec14(bl-succ)<return>
║│ __vgic_v3_clear_highest_active_priority:603.8 (vgic-v3-sr.c) Sbepe if (!║ap0 && !ap1) {
~ ║│ 0000ec1c: b9402fe8 ldr w8, [sp, #44]
║│ __vgic_v3_clear_highest_active_priority:603.12 (vgic-v3-sr.c) sbepe if (!ap0 ║&& !ap1) {
~ ║│ ┌────0000ec20: 35000128 cbnz w8, ec44 <__vgic_v3_clear_highest_active_priority+0x98>
║│ │
~ ║│ │ ┌─0000ec24: 14000001 b ec28 <__vgic_v3_clear_highest_active_priority+0x7c> <- 0000ec20(b.cc-succ)<fallthrough>
║│ │ │
║│ │ │ __vgic_v3_clear_highest_active_priority:603.16 (vgic-v3-sr.c) sbepe if (!ap0 && !║ap1) {
~ ║│ │ └>0000ec28: b9402be8 ldr w8, [sp, #40] <- 0000ec24(b)<__vgic_v3_clear_highest_active_priority+0x7c>
║│ │ __vgic_v3_clear_highest_active_priority:603.7 (vgic-v3-sr.c) sbepe if (║!ap0 && !ap1) {
~ ║│ │ ┌──0000ec2c: 350000c8 cbnz w8, ec44 <__vgic_v3_clear_highest_active_priority+0x98>
║│ │ │
~ ║│ │ │┌─0000ec30: 14000001 b ec34 <__vgic_v3_clear_highest_active_priority+0x88> <- 0000ec2c(b.cc-succ)<fallthrough>
║│ │ ││
║│ │ ││ __vgic_v3_clear_highest_active_priority:604.8 (vgic-v3-sr.c) Sbepe hap ║+= 32;
~ ║│ │ │└>0000ec34: b85d43a8 ldur w8, [x29, #-44] <- 0000ec30(b)<__vgic_v3_clear_highest_active_priority+0x88>
~ ║│ │ │ 0000ec38: 11008108 add w8, w8, #0x20
~ ║│ │ │ 0000ec3c: b81d43a8 stur w8, [x29, #-44]
║│ │ │ __vgic_v3_clear_highest_active_priority:605.4 (vgic-v3-sr.c) Sbepe ║continue;
~ ║│┌┼─┼──0000ec40: 14000051 b ed84 <__vgic_v3_clear_highest_active_priority+0x1d8>
║│││ │
║│││ │ __vgic_v3_clear_highest_active_priority:608.8 (vgic-v3-sr.c) Sbepe c0 = ║ap0 ? __ffs(ap0) : 32;
~ ║││└>└─>0000ec44: b9402fe8 ldr w8, [sp, #44] <- 0000ec20(b.cc)<__vgic_v3_clear_highest_active_priority+0x98>,0000ec2c(b.cc)<__vgic_v3_clear_highest_active_priority+0x98>
~ ║││ ┌──0000ec48: 34000148 cbz w8, ec70 <__vgic_v3_clear_highest_active_priority+0xc4>
║││ │
~ ║││ │┌─0000ec4c: 14000001 b ec50 <__vgic_v3_clear_highest_active_priority+0xa4> <- 0000ec48(b.cc-succ)<fallthrough>
║││ ││
║││ ││ __vgic_v3_clear_highest_active_priority:608.20 (vgic-v3-sr.c) sbepe c0 = ap0 ? __ffs(║ap0) : 32;
~ ║││ │└>0000ec50: b9402fe8 ldr w8, [sp, #44] <- 0000ec4c(b)<__vgic_v3_clear_highest_active_priority+0xa4>
~ ║││ │ 0000ec54: 2a0803e9 mov w9, w8
~ ║││ │ 0000ec58: f81f03a9 stur x9, [x29, #-16]
o: 0xec5c 0xec6c __ffs inlined from __vgic_v3_clear_highest_active_priority:608 (vgic-v3-sr.c) <a988d>:<lexical_block>:
o ║││ │ __ffs:13.24 (builtin-__ffs.h) Sbepe return __builtin_ctzl(║word);
+word param long unsigned int (base type, DW_ATE_unsigned size:8) 0xec5c 0xec6c (DW_OP_fbreg -0x10) __ffs(inlined):lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~o ║││ │ 0000ec5c: f85f03a9 ldur x9, [x29, #-16]
o ║││ │ __ffs:13.9 (builtin-__ffs.h) sbepe return ║__builtin_ctzl(word);
~o ║││ │ 0000ec60: dac00129 rbit x9, x9
~o ║││ │ 0000ec64: dac01129 clz x9, x9
~o ║││ │ 0000ec68: f9000fe9 str x9, [sp, #24]
-word param long unsigned int (base type, DW_ATE_unsigned size:8) 0xec5c 0xec6c (DW_OP_fbreg -0x10) __ffs(inlined):lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
║││ │ __vgic_v3_clear_highest_active_priority:608.8 (vgic-v3-sr.c) Sbepe c0 = ║ap0 ? __ffs(ap0) : 32;
~ ║││ ┌┼──0000ec6c: 14000005 b ec80 <__vgic_v3_clear_highest_active_priority+0xd4>
║││ ││
~ ║││ │└─>0000ec70: 52800408 mov w8, #0x20 // #32 <- 0000ec48(b.cc)<__vgic_v3_clear_highest_active_priority+0xc4>
~ ║││ │ 0000ec74: 2a0803e0 mov w0, w8
~ ║││ │ 0000ec78: f9000fe0 str x0, [sp, #24]
║││ │ __vgic_v3_clear_highest_active_priority:608.8 (vgic-v3-sr.c) sbepe c0 = ║ap0 ? __ffs(ap0) : 32;
~ ║││ │ ┌─0000ec7c: 14000001 b ec80 <__vgic_v3_clear_highest_active_priority+0xd4>
║││ │ │
~ ║││ └>└>0000ec80: f9400fe0 ldr x0, [sp, #24] <- 0000ec6c(b)<__vgic_v3_clear_highest_active_priority+0xd4>,0000ec7c(b)<__vgic_v3_clear_highest_active_priority+0xd4>
║││ __vgic_v3_clear_highest_active_priority:608.6 (vgic-v3-sr.c) sbepe c0 ║= ap0 ? __ffs(ap0) : 32;
~ ║││ 0000ec84: b90027e0 str w0, [sp, #36]
║││ __vgic_v3_clear_highest_active_priority:609.8 (vgic-v3-sr.c) Sbepe c1 = ║ap1 ? __ffs(ap1) : 32;
~ ║││ 0000ec88: b9402be8 ldr w8, [sp, #40]
~ ║││ ┌──0000ec8c: 34000148 cbz w8, ecb4 <__vgic_v3_clear_highest_active_priority+0x108>
║││ │
~ ║││ │┌─0000ec90: 14000001 b ec94 <__vgic_v3_clear_highest_active_priority+0xe8> <- 0000ec8c(b.cc-succ)<fallthrough>
║││ ││
║││ ││ __vgic_v3_clear_highest_active_priority:609.20 (vgic-v3-sr.c) sbepe c1 = ap1 ? __ffs(║ap1) : 32;
~ ║││ │└>0000ec94: b9402be8 ldr w8, [sp, #40] <- 0000ec90(b)<__vgic_v3_clear_highest_active_priority+0xe8>
~ ║││ │ 0000ec98: 2a0803e9 mov w9, w8
~ ║││ │ 0000ec9c: f81f83a9 stur x9, [x29, #-8]
p: 0xeca0 0xecb0 __ffs inlined from __vgic_v3_clear_highest_active_priority:609 (vgic-v3-sr.c) <a98ab>:<lexical_block>:
p ║││ │ __ffs:13.24 (builtin-__ffs.h) Sbepe return __builtin_ctzl(║word);
+word param long unsigned int (base type, DW_ATE_unsigned size:8) 0xeca0 0xecb0 (DW_OP_fbreg -0x8) __ffs(inlined):lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~p ║││ │ 0000eca0: f85f83a9 ldur x9, [x29, #-8]
p ║││ │ __ffs:13.9 (builtin-__ffs.h) sbepe return ║__builtin_ctzl(word);
~p ║││ │ 0000eca4: dac00129 rbit x9, x9
~p ║││ │ 0000eca8: dac01129 clz x9, x9
~p ║││ │ 0000ecac: f9000be9 str x9, [sp, #16]
-word param long unsigned int (base type, DW_ATE_unsigned size:8) 0xeca0 0xecb0 (DW_OP_fbreg -0x8) __ffs(inlined):lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
║││ │ __vgic_v3_clear_highest_active_priority:609.8 (vgic-v3-sr.c) Sbepe c1 = ║ap1 ? __ffs(ap1) : 32;
~ ║││ ┌┼──0000ecb0: 14000005 b ecc4 <__vgic_v3_clear_highest_active_priority+0x118>
║││ ││
~ ║││ │└─>0000ecb4: 52800408 mov w8, #0x20 // #32 <- 0000ec8c(b.cc)<__vgic_v3_clear_highest_active_priority+0x108>
~ ║││ │ 0000ecb8: 2a0803e0 mov w0, w8
~ ║││ │ 0000ecbc: f9000be0 str x0, [sp, #16]
║││ │ __vgic_v3_clear_highest_active_priority:609.8 (vgic-v3-sr.c) sbepe c1 = ║ap1 ? __ffs(ap1) : 32;
~ ║││ │ ┌─0000ecc0: 14000001 b ecc4 <__vgic_v3_clear_highest_active_priority+0x118>
║││ │ │
~ ║││ └>└>0000ecc4: f9400be0 ldr x0, [sp, #16] <- 0000ecb0(b)<__vgic_v3_clear_highest_active_priority+0x118>,0000ecc0(b)<__vgic_v3_clear_highest_active_priority+0x118>
║││ __vgic_v3_clear_highest_active_priority:609.6 (vgic-v3-sr.c) sbepe c1 ║= ap1 ? __ffs(ap1) : 32;
~ ║││ 0000ecc8: b90023e0 str w0, [sp, #32]
║││ __vgic_v3_clear_highest_active_priority:612.7 (vgic-v3-sr.c) Sbepe if (║c0 < c1) {
~ ║││ 0000eccc: b94027e8 ldr w8, [sp, #36]
║││ __vgic_v3_clear_highest_active_priority:612.12 (vgic-v3-sr.c) sbepe if (c0 < ║c1) {
~ ║││ 0000ecd0: b94023e9 ldr w9, [sp, #32]
║││ __vgic_v3_clear_highest_active_priority:612.7 (vgic-v3-sr.c) sbepe if (║c0 < c1) {
~ ║││ 0000ecd4: 6b090108 subs w8, w8, w9
~ ║││ ┌──0000ecd8: 5400026a b.ge ed24 <__vgic_v3_clear_highest_active_priority+0x178> // b.tcont
║││ │
~ ║││ │┌─0000ecdc: 14000001 b ece0 <__vgic_v3_clear_highest_active_priority+0x134> <- 0000ecd8(b.cc-succ)<fallthrough>
║││ ││
║││ ││ __vgic_v3_clear_highest_active_priority:613.12 (vgic-v3-sr.c) Sbepe ap0 &= ~║BIT(c0);
~ ║││ │└>0000ece0: b94027e8 ldr w8, [sp, #36] <- 0000ecdc(b)<__vgic_v3_clear_highest_active_priority+0x134>
~ ║││ │ 0000ece4: 2a0803e9 mov w9, w8
~ ║││ │ 0000ece8: 52800028 mov w8, #0x1 // #1
~ ║││ │ 0000ecec: 2a0803ea mov w10, w8
~ ║││ │ 0000ecf0: 9ac92149 lsl x9, x10, x9
║││ │ __vgic_v3_clear_highest_active_priority:613.8 (vgic-v3-sr.c) sbepe ap0 ║&= ~BIT(c0);
~ ║││ │ 0000ecf4: b9402fe8 ldr w8, [sp, #44]
~ ║││ │ 0000ecf8: 0a290108 bic w8, w8, w9
~ ║││ │ 0000ecfc: 2a0803e0 mov w0, w8
~ ║││ │ 0000ed00: b9002fe0 str w0, [sp, #44]
║││ │ __vgic_v3_clear_highest_active_priority:614.26 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap0rn(║ap0, i);
~ ║││ │ 0000ed04: b9402fe0 ldr w0, [sp, #44]
║││ │ __vgic_v3_clear_highest_active_priority:614.31 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap0rn(ap0, ║i);
~ ║││ │ 0000ed08: b94033e1 ldr w1, [sp, #48]
║││ │ __vgic_v3_clear_highest_active_priority:614.4 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap0rn(ap0, i);
~ ║││ │ 0000ed0c: 97fff866 bl cea4 <__vgic_v3_write_ap0rn>
║││ │
║││ │ __vgic_v3_clear_highest_active_priority:615.11 (vgic-v3-sr.c) Sbepe hap += ║c0;
~ ║││ │ 0000ed10: b94027e8 ldr w8, [sp, #36] <- 0000ed0c(bl-succ)<return>
║││ │ __vgic_v3_clear_highest_active_priority:615.8 (vgic-v3-sr.c) sbepe hap ║+= c0;
~ ║││ │ 0000ed14: b85d43a9 ldur w9, [x29, #-44]
~ ║││ │ 0000ed18: 0b080128 add w8, w9, w8
~ ║││ │ 0000ed1c: b81d43a8 stur w8, [x29, #-44]
║││ │ __vgic_v3_clear_highest_active_priority:616.3 (vgic-v3-sr.c) Sbepe ║} else {
~ ║││ ┌┼──0000ed20: 14000012 b ed68 <__vgic_v3_clear_highest_active_priority+0x1bc>
║││ ││
║││ ││ __vgic_v3_clear_highest_active_priority:617.12 (vgic-v3-sr.c) Sbepe ap1 &= ~║BIT(c1);
~ ║││ │└─>0000ed24: b94023e8 ldr w8, [sp, #32] <- 0000ecd8(b.cc)<__vgic_v3_clear_highest_active_priority+0x178>
~ ║││ │ 0000ed28: 2a0803e9 mov w9, w8
~ ║││ │ 0000ed2c: 52800028 mov w8, #0x1 // #1
~ ║││ │ 0000ed30: 2a0803ea mov w10, w8
~ ║││ │ 0000ed34: 9ac92149 lsl x9, x10, x9
║││ │ __vgic_v3_clear_highest_active_priority:617.8 (vgic-v3-sr.c) sbepe ap1 ║&= ~BIT(c1);
~ ║││ │ 0000ed38: b9402be8 ldr w8, [sp, #40]
~ ║││ │ 0000ed3c: 0a290108 bic w8, w8, w9
~ ║││ │ 0000ed40: 2a0803e0 mov w0, w8
~ ║││ │ 0000ed44: b9002be0 str w0, [sp, #40]
║││ │ __vgic_v3_clear_highest_active_priority:618.26 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap1rn(║ap1, i);
~ ║││ │ 0000ed48: b9402be0 ldr w0, [sp, #40]
║││ │ __vgic_v3_clear_highest_active_priority:618.31 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap1rn(ap1, ║i);
~ ║││ │ 0000ed4c: b94033e1 ldr w1, [sp, #48]
║││ │ __vgic_v3_clear_highest_active_priority:618.4 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap1rn(ap1, i);
~ ║││ │ 0000ed50: 97fff886 bl cf68 <__vgic_v3_write_ap1rn>
║││ │
║││ │ __vgic_v3_clear_highest_active_priority:619.11 (vgic-v3-sr.c) Sbepe hap += ║c1;
~ ║││ │ 0000ed54: b94023e8 ldr w8, [sp, #32] <- 0000ed50(bl-succ)<return>
║││ │ __vgic_v3_clear_highest_active_priority:619.8 (vgic-v3-sr.c) sbepe hap ║+= c1;
~ ║││ │ 0000ed58: b85d43a9 ldur w9, [x29, #-44]
~ ║││ │ 0000ed5c: 0b080128 add w8, w9, w8
~ ║││ │ 0000ed60: b81d43a8 stur w8, [x29, #-44]
~ ║││ │ ┌─0000ed64: 14000001 b ed68 <__vgic_v3_clear_highest_active_priority+0x1bc>
║││ │ │
║││ │ │ __vgic_v3_clear_highest_active_priority:623.10 (vgic-v3-sr.c) Sbepe return ║hap << __vgic_v3_bpr_min();
~ ║││ └>└>0000ed68: b85d43a8 ldur w8, [x29, #-44] <- 0000ed20(b)<__vgic_v3_clear_highest_active_priority+0x1bc>,0000ed64(b)<__vgic_v3_clear_highest_active_priority+0x1bc>
~ ║││ 0000ed6c: b9000fe8 str w8, [sp, #12]
║││ __vgic_v3_clear_highest_active_priority:623.17 (vgic-v3-sr.c) sbepe return hap << ║__vgic_v3_bpr_min();
~ ║││ 0000ed70: 97ffff64 bl eb00 <__vgic_v3_bpr_min>
║││
~ ║││ 0000ed74: b9400fe8 ldr w8, [sp, #12] <- 0000ed70(bl-succ)<return>
║││ __vgic_v3_clear_highest_active_priority:623.14 (vgic-v3-sr.c) sbepe return hap ║<< __vgic_v3_bpr_min();
~ ║││ 0000ed78: 1ac02108 lsl w8, w8, w0
║││ __vgic_v3_clear_highest_active_priority:623.3 (vgic-v3-sr.c) sbepe ║return hap << __vgic_v3_bpr_min();
~ ║││ 0000ed7c: b81ec3a8 stur w8, [x29, #-20]
~ ║││ ┌───0000ed80: 14000008 b eda0 <__vgic_v3_clear_highest_active_priority+0x1f4>
-ap0 var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xec04 0xed84 (DW_OP_breg31 0x2c) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:598
-ap1 var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xec04 0xed84 (DW_OP_breg31 0x28) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:598
-c0 var int (base type, DW_ATE_signed size:4) 0xec04 0xed84 (DW_OP_breg31 0x24) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:599
-c1 var int (base type, DW_ATE_signed size:4) 0xec04 0xed84 (DW_OP_breg31 0x20) lexblock:__vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:599
║││ │
║││ │ __vgic_v3_clear_highest_active_priority:597.32 (vgic-v3-sr.c) Sbepe for (i = 0; i < nr_apr_regs; i║++) {
~ ║│└─┼──>0000ed84: b94033e8 ldr w8, [sp, #48] <- 0000ec40(b)<__vgic_v3_clear_highest_active_priority+0x1d8>
~ ║│ │ 0000ed88: 11000508 add w8, w8, #0x1
~ ║│ │ 0000ed8c: b90033e8 str w8, [sp, #48]
║│ │ __vgic_v3_clear_highest_active_priority:597.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i < nr_apr_regs; i++) {
~ ╚╪══╪═══0000ed90: 17ffff98 b ebf0 <__vgic_v3_clear_highest_active_priority+0x44>
│ │
~ └──┼──>0000ed94: 52801fe8 mov w8, #0xff // #255 <- 0000ebfc(b.cc)<__vgic_v3_clear_highest_active_priority+0x1e8>
│ __vgic_v3_clear_highest_active_priority:626.2 (vgic-v3-sr.c) Sbepe ║return GICv3_IDLE_PRIORITY;
~ │ 0000ed98: b81ec3a8 stur w8, [x29, #-20]
~ │ ┌─0000ed9c: 14000001 b eda0 <__vgic_v3_clear_highest_active_priority+0x1f4>
│ │
│ │ __vgic_v3_clear_highest_active_priority:627.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000eda0: b85ec3a0 ldur w0, [x29, #-20] <- 0000ed80(b)<__vgic_v3_clear_highest_active_priority+0x1f4>,0000ed9c(b)<__vgic_v3_clear_highest_active_priority+0x1f4>
~ 0000eda4: a9467bfd ldp x29, x30, [sp, #96]
~ 0000eda8: 9101c3ff add sp, sp, #0x70
0000ebb8 CFA:r29+16 r29:c-16 r30:c-8
~ 0000edac: d65f03c0 ret
-nr_apr_regs var typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xebac 0xedb0 (DW_OP_fbreg -0x18) __vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:593
-hap var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xebac 0xedb0 (DW_OP_fbreg -0x2c) __vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:594
-i var int (base type, DW_ATE_signed size:4) 0xebac 0xedb0 (DW_OP_breg31 0x30) __vgic_v3_clear_highest_active_priority:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:595
**0000edb0 <__vgic_v3_find_active_lr>:
+ __vgic_v3_find_active_lr params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xedb0 0xee7c (DW_OP_fbreg -0x10)
+intid param int (base type, DW_ATE_signed size:4) 0xedb0 0xee7c (DW_OP_fbreg -0x14)
+lr_val param pointer(typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8)))) 0xedb0 0xee7c (DW_OP_breg31 0x10)
__vgic_v3_find_active_lr:480.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xedb0 0xee7c (DW_OP_fbreg -0x10) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:478
+intid param int (base type, DW_ATE_signed size:4) 0xedb0 0xee7c (DW_OP_fbreg -0x14) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:478
+lr_val param pointer(typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8)))) 0xedb0 0xee7c (DW_OP_breg31 0x10) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:479
+used_lrs var unsigned int (base type, DW_ATE_unsigned size:4) 0xedb0 0xee7c (DW_OP_breg31 0xc) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:481
+i var int (base type, DW_ATE_signed size:4) 0xedb0 0xee7c (DW_OP_breg31 0x8) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:482
~ 0000edb0: d10103ff sub sp, sp, #0x40 <- 0000da84(bl)<__vgic_v3_find_active_lr>,0000e314(bl)<__vgic_v3_find_active_lr>
~ 0000edb4: a9037bfd stp x29, x30, [sp, #48]
0000edb0 CFA:r31 r29:u r30:u
~ 0000edb8: 9100c3fd add x29, sp, #0x30
~ 0000edbc: f81f03a0 stur x0, [x29, #-16]
~ 0000edc0: b81ec3a1 stur w1, [x29, #-20]
~ 0000edc4: f9000be2 str x2, [sp, #16]
__vgic_v3_find_active_lr:481.26 (vgic-v3-sr.c) SbePe unsigned int used_lrs = ║vcpu->arch.vgic_cpu.vgic_v3.used_lrs;
~ 0000edc8: f85f03a8 ldur x8, [x29, #-16]
__vgic_v3_find_active_lr:481.54 (vgic-v3-sr.c) sbepe unsigned int used_lrs = vcpu->arch.vgic_cpu.vgic_v3.║used_lrs;
~ 0000edcc: b9500909 ldr w9, [x8, #4104]
__vgic_v3_find_active_lr:481.15 (vgic-v3-sr.c) sbepe unsigned int ║used_lrs = vcpu->arch.vgic_cpu.vgic_v3.used_lrs;
~ 0000edd0: b9000fe9 str w9, [sp, #12]
~ 0000edd4: 2a1f03e9 mov w9, wzr
__vgic_v3_find_active_lr:484.9 (vgic-v3-sr.c) Sbepe for (i ║= 0; i < used_lrs; i++) {
~ 0000edd8: b9000be9 str w9, [sp, #8]
__vgic_v3_find_active_lr:484.7 (vgic-v3-sr.c) sbepe for (║i = 0; i < used_lrs; i++) {
~ ┌─0000eddc: 14000001 b ede0 <__vgic_v3_find_active_lr+0x30>
│
│ __vgic_v3_find_active_lr:484.14 (vgic-v3-sr.c) sbepe for (i = 0; ║i < used_lrs; i++) {
~ ╔═════>└>0000ede0: b9400be8 ldr w8, [sp, #8] <- 0000eddc(b)<__vgic_v3_find_active_lr+0x30>,v0000ee4c(b)<__vgic_v3_find_active_lr+0x30>
║ __vgic_v3_find_active_lr:484.18 (vgic-v3-sr.c) sbepe for (i = 0; i < ║used_lrs; i++) {
~ ║ 0000ede4: b9400fe9 ldr w9, [sp, #12]
║ __vgic_v3_find_active_lr:484.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i < used_lrs; i++) {
~ ║ 0000ede8: 6b090108 subs w8, w8, w9
~ ║┌───────0000edec: 54000322 b.cs ee50 <__vgic_v3_find_active_lr+0xa0> // b.hs, b.nlast
║│
~ ║│ ┌─0000edf0: 14000001 b edf4 <__vgic_v3_find_active_lr+0x44> <- 0000edec(b.cc-succ)<fallthrough>
║│ │
║│ │ __vgic_v3_find_active_lr:485.29 (vgic-v3-sr.c) Sbepe u64 val = __gic_v3_get_lr(║i);
+val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xedf4 0xee40 (DW_OP_breg31 0x0) lexblock:__vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:485
~ ║│ └>0000edf4: b9400be0 ldr w0, [sp, #8] <- 0000edf0(b)<__vgic_v3_find_active_lr+0x44>
║│ __vgic_v3_find_active_lr:485.13 (vgic-v3-sr.c) sbepe u64 val = ║__gic_v3_get_lr(i);
~ ║│ 0000edf8: 97fff56e bl c3b0 <__gic_v3_get_lr>
║│
║│ __vgic_v3_find_active_lr:485.7 (vgic-v3-sr.c) sbepe u64 ║val = __gic_v3_get_lr(i);
~ ║│ 0000edfc: f90003e0 str x0, [sp] <- 0000edf8(bl-succ)<return>
║│ __vgic_v3_find_active_lr:487.8 (vgic-v3-sr.c) Sbepe if ((║val & ICH_LR_VIRTUAL_ID_MASK) == intid &&
~ ║│ 0000ee00: b94003e8 ldr w8, [sp]
~ ║│ 0000ee04: 2a0803e9 mov w9, w8
║│ __vgic_v3_find_active_lr:487.41 (vgic-v3-sr.c) sbepe if ((val & ICH_LR_VIRTUAL_ID_MASK) == ║intid &&
~ ║│ 0000ee08: b89ec3aa ldursw x10, [x29, #-20]
║│ __vgic_v3_find_active_lr:487.47 (vgic-v3-sr.c) sbepe if ((val & ICH_LR_VIRTUAL_ID_MASK) == intid &&
~ ║│ 0000ee0c: eb0a0129 subs x9, x9, x10
~ ║│ ┌─────0000ee10: 54000161 b.ne ee3c <__vgic_v3_find_active_lr+0x8c> // b.any
║│ │
~ ║│ │ ┌─0000ee14: 14000001 b ee18 <__vgic_v3_find_active_lr+0x68> <- 0000ee10(b.cc-succ)<fallthrough>
║│ │ │
║│ │ │ __vgic_v3_find_active_lr:487.7 (vgic-v3-sr.c) sbepe if (║(val & ICH_LR_VIRTUAL_ID_MASK) == intid &&
~ ║│ │ └>0000ee18: 39401fe8 ldrb w8, [sp, #7] <- 0000ee14(b)<__vgic_v3_find_active_lr+0x68>
~ ║│ │ ┌───0000ee1c: 36380108 tbz w8, #7, ee3c <__vgic_v3_find_active_lr+0x8c>
║│ │ │
~ ║│ │ │ ┌─0000ee20: 14000001 b ee24 <__vgic_v3_find_active_lr+0x74> <- 0000ee1c(b.cc-succ)<fallthrough>
║│ │ │ │
║│ │ │ │ __vgic_v3_find_active_lr:489.14 (vgic-v3-sr.c) Sbepe *lr_val = ║val;
~ ║│ │ │ └>0000ee24: f94003e8 ldr x8, [sp] <- 0000ee20(b)<__vgic_v3_find_active_lr+0x74>
║│ │ │ __vgic_v3_find_active_lr:489.5 (vgic-v3-sr.c) sbepe *║lr_val = val;
~ ║│ │ │ 0000ee28: f9400be9 ldr x9, [sp, #16]
║│ │ │ __vgic_v3_find_active_lr:489.12 (vgic-v3-sr.c) sbepe *lr_val ║= val;
~ ║│ │ │ 0000ee2c: f9000128 str x8, [x9]
║│ │ │ __vgic_v3_find_active_lr:490.11 (vgic-v3-sr.c) Sbepe return i;
~ ║│ │ │ 0000ee30: b9400bea ldr w10, [sp, #8]
║│ │ │ __vgic_v3_find_active_lr:490.4 (vgic-v3-sr.c) sbepe ║return i;
~ ║│ │ │ 0000ee34: b81fc3aa stur w10, [x29, #-4]
~ ║│┌┼─┼───0000ee38: 1400000d b ee6c <__vgic_v3_find_active_lr+0xbc>
║│││ │
║│││ │ __vgic_v3_find_active_lr:492.2 (vgic-v3-sr.c) Sbepe }
~ ║││└>└>┌─0000ee3c: 14000001 b ee40 <__vgic_v3_find_active_lr+0x90> <- 0000ee10(b.cc)<__vgic_v3_find_active_lr+0x8c>,0000ee1c(b.cc)<__vgic_v3_find_active_lr+0x8c>
-val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xedf4 0xee40 (DW_OP_breg31 0x0) lexblock:__vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:485
║││ │
║││ │ __vgic_v3_find_active_lr:484.29 (vgic-v3-sr.c) Sbepe for (i = 0; i < used_lrs; i║++) {
~ ║││ └>0000ee40: b9400be8 ldr w8, [sp, #8] <- 0000ee3c(b)<__vgic_v3_find_active_lr+0x90>
~ ║││ 0000ee44: 11000508 add w8, w8, #0x1
~ ║││ 0000ee48: b9000be8 str w8, [sp, #8]
║││ __vgic_v3_find_active_lr:484.2 (vgic-v3-sr.c) sbepe ║for (i = 0; i < used_lrs; i++) {
~ ╚╪╪══════0000ee4c: 17ffffe5 b ede0 <__vgic_v3_find_active_lr+0x30>
││
││ __vgic_v3_find_active_lr:494.3 (vgic-v3-sr.c) Sbepe *║lr_val = ICC_IAR1_EL1_SPURIOUS;
~ └┼─────>0000ee50: f9400be8 ldr x8, [sp, #16] <- 0000edec(b.cc)<__vgic_v3_find_active_lr+0xa0>
~ │ 0000ee54: 52807fe9 mov w9, #0x3ff // #1023
~ │ 0000ee58: 2a0903ea mov w10, w9
│ __vgic_v3_find_active_lr:494.10 (vgic-v3-sr.c) sbepe *lr_val ║= ICC_IAR1_EL1_SPURIOUS;
~ │ 0000ee5c: f900010a str x10, [x8]
~ │ 0000ee60: 12800009 mov w9, #0xffffffff // #-1
│ __vgic_v3_find_active_lr:495.2 (vgic-v3-sr.c) Sbepe ║return -1;
~ │ 0000ee64: b81fc3a9 stur w9, [x29, #-4]
~ │ ┌─0000ee68: 14000001 b ee6c <__vgic_v3_find_active_lr+0xbc>
│ │
│ │ __vgic_v3_find_active_lr:496.1 (vgic-v3-sr.c) Sbepe ║}
~ └───>└>0000ee6c: b85fc3a0 ldur w0, [x29, #-4] <- 0000ee38(b)<__vgic_v3_find_active_lr+0xbc>,0000ee68(b)<__vgic_v3_find_active_lr+0xbc>
~ 0000ee70: a9437bfd ldp x29, x30, [sp, #48]
~ 0000ee74: 910103ff add sp, sp, #0x40
0000edbc CFA:r29+16 r29:c-16 r30:c-8
~ 0000ee78: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xedb0 0xee7c (DW_OP_fbreg -0x10) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:478
-intid param int (base type, DW_ATE_signed size:4) 0xedb0 0xee7c (DW_OP_fbreg -0x14) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:478
-lr_val param pointer(typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8)))) 0xedb0 0xee7c (DW_OP_breg31 0x10) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:479
-used_lrs var unsigned int (base type, DW_ATE_unsigned size:4) 0xedb0 0xee7c (DW_OP_breg31 0xc) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:481
-i var int (base type, DW_ATE_signed size:4) 0xedb0 0xee7c (DW_OP_breg31 0x8) __vgic_v3_find_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:482
**0000ee7c <__vgic_v3_bump_eoicount>:
+ __vgic_v3_bump_eoicount params: none
__vgic_v3_bump_eoicount:679.0 (vgic-v3-sr.c) Sbepe ║{
0000ee7c CFA:r31
+hcr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xee7c 0xeecc (DW_OP_fbreg 0x1c) __vgic_v3_bump_eoicount:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:680
~ 0000ee7c: d10083ff sub sp, sp, #0x20 <- 0000da9c(bl)<__vgic_v3_bump_eoicount>,0000e32c(bl)<__vgic_v3_bump_eoicount>
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xee80 0xee94 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_bump_eoicount:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:682
~ 0000ee80: d53ccb08 mrs x8, s3_4_c12_c11_0
__vgic_v3_bump_eoicount:682.8 (vgic-v3-sr.c) SbePe hcr = ║read_gicreg(ICH_HCR_EL2);
~ 0000ee84: f9000be8 str x8, [sp, #16]
~ 0000ee88: f9400be8 ldr x8, [sp, #16]
~ 0000ee8c: f90007e8 str x8, [sp, #8]
~ 0000ee90: f94007e8 ldr x8, [sp, #8]
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xee80 0xee94 (DW_OP_fbreg 0x10) lexblock:__vgic_v3_bump_eoicount:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:682
__vgic_v3_bump_eoicount:682.6 (vgic-v3-sr.c) sbepe hcr ║= read_gicreg(ICH_HCR_EL2);
~ 0000ee94: b9001fe8 str w8, [sp, #28]
__vgic_v3_bump_eoicount:683.6 (vgic-v3-sr.c) Sbepe hcr ║+= 1 << ICH_HCR_EOIcount_SHIFT;
~ 0000ee98: b9401fe8 ldr w8, [sp, #28]
~ 0000ee9c: 52a10009 mov w9, #0x8000000 // #134217728
~ 0000eea0: 0b090108 add w8, w8, w9
~ 0000eea4: b9001fe8 str w8, [sp, #28]
__vgic_v3_bump_eoicount:684.2 (vgic-v3-sr.c) Sbepe ║write_gicreg(hcr, ICH_HCR_EL2);
~ ┌─0000eea8: 14000001 b eeac <__vgic_v3_bump_eoicount+0x30>
│
│ __vgic_v3_bump_eoicount:684.2 (vgic-v3-sr.c) sbepe ║write_gicreg(hcr, ICH_HCR_EL2);
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xeeac 0xeec4 (DW_OP_fbreg 0x0) lexblock:__vgic_v3_bump_eoicount:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:684
~ └>0000eeac: b9401fe8 ldr w8, [sp, #28] <- 0000eea8(b)<__vgic_v3_bump_eoicount+0x30>
~ 0000eeb0: 2a0803e9 mov w9, w8
~ 0000eeb4: f90003e9 str x9, [sp]
~ 0000eeb8: f94003e9 ldr x9, [sp]
~ 0000eebc: d51ccb09 msr s3_4_c12_c11_0, x9
~ ┌─0000eec0: 14000001 b eec4 <__vgic_v3_bump_eoicount+0x48>
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xeeac 0xeec4 (DW_OP_fbreg 0x0) lexblock:__vgic_v3_bump_eoicount:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:684
│
│ __vgic_v3_bump_eoicount:685.1 (vgic-v3-sr.c) Sbepe ║}
~ └>0000eec4: 910083ff add sp, sp, #0x20 <- 0000eec0(b)<__vgic_v3_bump_eoicount+0x48>
0000ee80 CFA:r31+32
~ 0000eec8: d65f03c0 ret
-hcr var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xee7c 0xeecc (DW_OP_fbreg 0x1c) __vgic_v3_bump_eoicount:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:680
**0000eecc <__vgic_v3_clear_active_lr>:
+ __vgic_v3_clear_active_lr params:
+lr param int (base type, DW_ATE_signed size:4) 0xeecc 0xef40 (DW_OP_fbreg -0x14)
+lr_val param typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xeecc 0xef40 (DW_OP_breg31 0x10)
__vgic_v3_clear_active_lr:666.0 (vgic-v3-sr.c) Sbepe ║{
+lr param int (base type, DW_ATE_signed size:4) 0xeecc 0xef40 (DW_OP_fbreg -0x14) __vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:665
+lr_val param typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xeecc 0xef40 (DW_OP_breg31 0x10) __vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:665
~ 0000eecc: d10103ff sub sp, sp, #0x40 <- 0000daf4(bl)<__vgic_v3_clear_active_lr>,0000e33c(bl)<__vgic_v3_clear_active_lr>
~ 0000eed0: a9037bfd stp x29, x30, [sp, #48]
0000eecc CFA:r31 r29:u r30:u
~ 0000eed4: 9100c3fd add x29, sp, #0x30
~ 0000eed8: b81ec3a0 stur w0, [x29, #-20]
~ 0000eedc: f9000be1 str x1, [sp, #16]
__vgic_v3_clear_active_lr:667.9 (vgic-v3-sr.c) SbePe lr_val ║&= ~ICH_LR_ACTIVE_BIT;
~ 0000eee0: f9400be8 ldr x8, [sp, #16]
~ 0000eee4: 9240f908 and x8, x8, #0x7fffffffffffffff
~ 0000eee8: f9000be8 str x8, [sp, #16]
__vgic_v3_clear_active_lr:668.6 (vgic-v3-sr.c) Sbepe if (║lr_val & ICH_LR_HW) {
~ 0000eeec: 39405fe9 ldrb w9, [sp, #23]
~ ┌───0000eef0: 362801c9 tbz w9, #5, ef28 <__vgic_v3_clear_active_lr+0x5c>
│
~ │ ┌─0000eef4: 14000001 b eef8 <__vgic_v3_clear_active_lr+0x2c> <- 0000eef0(b.cc-succ)<fallthrough>
│ │
│ │ __vgic_v3_clear_active_lr:671.10 (vgic-v3-sr.c) Sbepe pid = (║lr_val & ICH_LR_PHYS_ID_MASK) >> ICH_LR_PHYS_ID_SHIFT;
+pid var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xeef8 0xef28 (DW_OP_breg31 0xc) lexblock:__vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:669
~ │ └>0000eef8: f9400be8 ldr x8, [sp, #16] <- 0000eef4(b)<__vgic_v3_clear_active_lr+0x2c>
│ __vgic_v3_clear_active_lr:671.40 (vgic-v3-sr.c) sbepe pid = (lr_val & ICH_LR_PHYS_ID_MASK) ║>> ICH_LR_PHYS_ID_SHIFT;
~ │ 0000eefc: d360a508 ubfx x8, x8, #32, #10
│ __vgic_v3_clear_active_lr:671.7 (vgic-v3-sr.c) sbepe pid ║= (lr_val & ICH_LR_PHYS_ID_MASK) >> ICH_LR_PHYS_ID_SHIFT;
~ │ 0000ef00: b9000fe8 str w8, [sp, #12]
│ __vgic_v3_clear_active_lr:672.17 (vgic-v3-sr.c) Sbepe gic_write_dir(║pid);
~ │ 0000ef04: b9400fe8 ldr w8, [sp, #12]
~ │ 0000ef08: b81fc3a8 stur w8, [x29, #-4]
q: 0xef0c 0xef24 gic_write_dir inlined from __vgic_v3_clear_active_lr:672 (vgic-v3-sr.c) <a9a1f>:<lexical_block>:
q │ gic_write_dir:37.2 (arch_gicv3.h) Sbepe ║write_sysreg_s(irq, SYS_ICC_DIR_EL1);
+irq param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xef0c 0xef24 (DW_OP_fbreg -0x4) gic_write_dir(inlined):lexblock:__vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xef0c 0xef20 (DW_OP_fbreg -0x10) lexblock:gic_write_dir(inlined):lexblock:__vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~q │ 0000ef0c: b85fc3a8 ldur w8, [x29, #-4]
~q │ 0000ef10: 2a0803e9 mov w9, w8
~q │ 0000ef14: f81f03a9 stur x9, [x29, #-16]
~q │ 0000ef18: f85f03a9 ldur x9, [x29, #-16]
~q │ 0000ef1c: d518cb29 msr s3_0_c12_c11_1, x9
-__val var typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xef0c 0xef20 (DW_OP_fbreg -0x10) lexblock:gic_write_dir(inlined):lexblock:__vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
q │ gic_write_dir:38.2 (arch_gicv3.h) Sbepe ║isb();
~q │ 0000ef20: d5033fdf isb
-irq param typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xef0c 0xef24 (DW_OP_fbreg -0x4) gic_write_dir(inlined):lexblock:__vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ __vgic_v3_clear_active_lr:673.2 (vgic-v3-sr.c) Sbepe }
~ │ ┌─0000ef24: 14000001 b ef28 <__vgic_v3_clear_active_lr+0x5c>
-pid var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xeef8 0xef28 (DW_OP_breg31 0xc) lexblock:__vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:669
│ │
│ │ __vgic_v3_clear_active_lr:675.18 (vgic-v3-sr.c) Sbepe __gic_v3_set_lr(║lr_val, lr);
~ └>└>0000ef28: f9400be0 ldr x0, [sp, #16] <- 0000eef0(b.cc)<__vgic_v3_clear_active_lr+0x5c>,0000ef24(b)<__vgic_v3_clear_active_lr+0x5c>
__vgic_v3_clear_active_lr:675.26 (vgic-v3-sr.c) sbepe __gic_v3_set_lr(lr_val, ║lr);
~ 0000ef2c: b85ec3a1 ldur w1, [x29, #-20]
__vgic_v3_clear_active_lr:675.2 (vgic-v3-sr.c) sbepe ║__gic_v3_set_lr(lr_val, lr);
~ 0000ef30: 97fff5a5 bl c5c4 <__gic_v3_set_lr>
__vgic_v3_clear_active_lr:676.1 (vgic-v3-sr.c) Sbepe ║}
~ 0000ef34: a9437bfd ldp x29, x30, [sp, #48] <- 0000ef30(bl-succ)<return>
~ 0000ef38: 910103ff add sp, sp, #0x40
0000eed8 CFA:r29+16 r29:c-16 r30:c-8
~ 0000ef3c: d65f03c0 ret
-lr param int (base type, DW_ATE_signed size:4) 0xeecc 0xef40 (DW_OP_fbreg -0x14) __vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:665
-lr_val param typedef(u64=typedef(__u64=long long unsigned int (base type, DW_ATE_unsigned size:8))) 0xeecc 0xef40 (DW_OP_breg31 0x10) __vgic_v3_clear_active_lr:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:665
**0000ef40 <__vgic_v3_read_apxrn>:
+ __vgic_v3_read_apxrn params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xef40 0xefdc (DW_OP_breg31 0x10)
+rt param int (base type, DW_ATE_signed size:4) 0xef40 0xefdc (DW_OP_breg31 0xc)
+n param int (base type, DW_ATE_signed size:4) 0xef40 0xefdc (DW_OP_breg31 0x8)
__vgic_v3_read_apxrn:829.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xef40 0xefdc (DW_OP_breg31 0x10) __vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:828
+rt param int (base type, DW_ATE_signed size:4) 0xef40 0xefdc (DW_OP_breg31 0xc) __vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:828
+n param int (base type, DW_ATE_signed size:4) 0xef40 0xefdc (DW_OP_breg31 0x8) __vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:828
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xef40 0xefdc (DW_OP_breg31 0x4) __vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:830
~ 0000ef40: d10103ff sub sp, sp, #0x40 <- 0000ddb4(bl)<__vgic_v3_read_apxrn>,0000de1c(bl)<__vgic_v3_read_apxrn>,0000de84(bl)<__vgic_v3_read_apxrn>,0000deec(bl)<__vgic_v3_read_apxrn>
~ 0000ef44: a9037bfd stp x29, x30, [sp, #48]
0000ef40 CFA:r31 r29:u r30:u
~ 0000ef48: 9100c3fd add x29, sp, #0x30
~ 0000ef4c: f9000be0 str x0, [sp, #16]
~ 0000ef50: b9000fe1 str w1, [sp, #12]
~ 0000ef54: b9000be2 str w2, [sp, #8]
__vgic_v3_read_apxrn:832.27 (vgic-v3-sr.c) SbePe if (!__vgic_v3_get_group(║vcpu))
~ 0000ef58: f9400be0 ldr x0, [sp, #16]
__vgic_v3_read_apxrn:832.7 (vgic-v3-sr.c) sbepe if (!║__vgic_v3_get_group(vcpu))
~ 0000ef5c: 97fffdff bl e758 <__vgic_v3_get_group>
__vgic_v3_read_apxrn:832.6 (vgic-v3-sr.c) sbepe if (║!__vgic_v3_get_group(vcpu))
~ ┌──0000ef60: 350000c0 cbnz w0, ef78 <__vgic_v3_read_apxrn+0x38> <- 0000ef5c(bl-succ)<return>
│
~ │┌─0000ef64: 14000001 b ef68 <__vgic_v3_read_apxrn+0x28> <- 0000ef60(b.cc-succ)<fallthrough>
││
││ __vgic_v3_read_apxrn:833.30 (vgic-v3-sr.c) Sbepe val = __vgic_v3_read_ap0rn(║n);
~ │└>0000ef68: b9400be0 ldr w0, [sp, #8] <- 0000ef64(b)<__vgic_v3_read_apxrn+0x28>
│ __vgic_v3_read_apxrn:833.9 (vgic-v3-sr.c) sbepe val = ║__vgic_v3_read_ap0rn(n);
~ │ 0000ef6c: 97fff727 bl cc08 <__vgic_v3_read_ap0rn>
│
│ __vgic_v3_read_apxrn:833.7 (vgic-v3-sr.c) sbepe val ║= __vgic_v3_read_ap0rn(n);
~ │ 0000ef70: b90007e0 str w0, [sp, #4] <- 0000ef6c(bl-succ)<return>
│ __vgic_v3_read_apxrn:833.3 (vgic-v3-sr.c) sbepe ║val = __vgic_v3_read_ap0rn(n);
~ ┌┼──0000ef74: 14000005 b ef88 <__vgic_v3_read_apxrn+0x48>
││
││ __vgic_v3_read_apxrn:835.30 (vgic-v3-sr.c) Sbepe val = __vgic_v3_read_ap1rn(║n);
~ │└─>0000ef78: b9400be0 ldr w0, [sp, #8] <- 0000ef60(b.cc)<__vgic_v3_read_apxrn+0x38>
│ __vgic_v3_read_apxrn:835.9 (vgic-v3-sr.c) sbepe val = ║__vgic_v3_read_ap1rn(n);
~ │ 0000ef7c: 97fff751 bl ccc0 <__vgic_v3_read_ap1rn>
│
│ __vgic_v3_read_apxrn:835.7 (vgic-v3-sr.c) sbepe val ║= __vgic_v3_read_ap1rn(n);
~ │ 0000ef80: b90007e0 str w0, [sp, #4] <- 0000ef7c(bl-succ)<return>
~ │ ┌─0000ef84: 14000001 b ef88 <__vgic_v3_read_apxrn+0x48>
│ │
│ │ __vgic_v3_read_apxrn:837.15 (vgic-v3-sr.c) Sbepe vcpu_set_reg(║vcpu, rt, val);
~ └>└>0000ef88: f9400be8 ldr x8, [sp, #16] <- 0000ef74(b)<__vgic_v3_read_apxrn+0x48>,0000ef84(b)<__vgic_v3_read_apxrn+0x48>
__vgic_v3_read_apxrn:837.21 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, ║rt, val);
~ 0000ef8c: b9400fe9 ldr w9, [sp, #12]
__vgic_v3_read_apxrn:837.25 (vgic-v3-sr.c) sbepe vcpu_set_reg(vcpu, rt, ║val);
~ 0000ef90: b94007ea ldr w10, [sp, #4]
~ 0000ef94: 2a0a03eb mov w11, w10
~ 0000ef98: f81f83a8 stur x8, [x29, #-8]
~ 0000ef9c: 381f43a9 sturb w9, [x29, #-12]
~ 0000efa0: f9000feb str x11, [sp, #24]
r: 0xefa4 0xefd0 vcpu_set_reg inlined from __vgic_v3_read_apxrn:837 (vgic-v3-sr.c) <a9aa7>:
r vcpu_set_reg:172.6 (kvm_emulate.h) Sbepe if (║reg_num != 31)
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xefa4 0xefd0 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xefa4 0xefd0 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xefa4 0xefd0 (DW_OP_breg31 0x18) vcpu_set_reg(inlined):__vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~r 0000efa4: 385f43a9 ldurb w9, [x29, #-12]
r vcpu_set_reg:172.6 (kvm_emulate.h) sbepe if (║reg_num != 31)
~r 0000efa8: 71007d29 subs w9, w9, #0x1f
~r ┌───0000efac: 54000120 b.eq efd0 <__vgic_v3_read_apxrn+0x90> // b.none
│
~r │ ┌─0000efb0: 14000001 b efb4 <__vgic_v3_read_apxrn+0x74> <- 0000efac(b.cc-succ)<fallthrough>
│ │
r │ │ vcpu_set_reg:173.39 (kvm_emulate.h) Sbepe vcpu_gp_regs(vcpu)->regs[reg_num] = ║val;
~r │ └>0000efb4: f9400fe8 ldr x8, [sp, #24] <- 0000efb0(b)<__vgic_v3_read_apxrn+0x74>
r │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~r │ 0000efb8: f85f83a9 ldur x9, [x29, #-8]
r │ vcpu_set_reg:173.28 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[║reg_num] = val;
~r │ 0000efbc: 385f43aa ldurb w10, [x29, #-12]
~r │ 0000efc0: 2a0a03eb mov w11, w10
r │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~r │ 0000efc4: 8b0b0d29 add x9, x9, x11, lsl #3
r │ vcpu_set_reg:173.37 (kvm_emulate.h) sbepe vcpu_gp_regs(vcpu)->regs[reg_num] ║= val;
~r │ 0000efc8: f900b128 str x8, [x9, #352]
r │ vcpu_set_reg:173.3 (kvm_emulate.h) sbepe ║vcpu_gp_regs(vcpu)->regs[reg_num] = val;
~r │ ┌─0000efcc: 14000001 b efd0 <__vgic_v3_read_apxrn+0x90>
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xefa4 0xefd0 (DW_OP_fbreg -0x8) vcpu_set_reg(inlined):__vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xefa4 0xefd0 (DW_OP_fbreg -0xc) vcpu_set_reg(inlined):__vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-val param long unsigned int (base type, DW_ATE_unsigned size:8) 0xefa4 0xefd0 (DW_OP_breg31 0x18) vcpu_set_reg(inlined):__vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
│ │ __vgic_v3_read_apxrn:838.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000efd0: a9437bfd ldp x29, x30, [sp, #48] <- 0000efac(b.cc)<__vgic_v3_read_apxrn+0x90>,0000efcc(b)<__vgic_v3_read_apxrn+0x90>
~ 0000efd4: 910103ff add sp, sp, #0x40
0000ef4c CFA:r29+16 r29:c-16 r30:c-8
~ 0000efd8: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xef40 0xefdc (DW_OP_breg31 0x10) __vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:828
-rt param int (base type, DW_ATE_signed size:4) 0xef40 0xefdc (DW_OP_breg31 0xc) __vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:828
-n param int (base type, DW_ATE_signed size:4) 0xef40 0xefdc (DW_OP_breg31 0x8) __vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:828
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xef40 0xefdc (DW_OP_breg31 0x4) __vgic_v3_read_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:830
**0000efdc <__vgic_v3_write_apxrn>:
+ __vgic_v3_write_apxrn params:
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xefdc 0xf080 (DW_OP_breg31 0x18)
+rt param int (base type, DW_ATE_signed size:4) 0xefdc 0xf080 (DW_OP_breg31 0x14)
+n param int (base type, DW_ATE_signed size:4) 0xefdc 0xf080 (DW_OP_breg31 0x10)
__vgic_v3_write_apxrn:841.0 (vgic-v3-sr.c) Sbepe ║{
+vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xefdc 0xf080 (DW_OP_breg31 0x18) __vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:840
+rt param int (base type, DW_ATE_signed size:4) 0xefdc 0xf080 (DW_OP_breg31 0x14) __vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:840
+n param int (base type, DW_ATE_signed size:4) 0xefdc 0xf080 (DW_OP_breg31 0x10) __vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:840
+val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xefdc 0xf080 (DW_OP_breg31 0xc) __vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:842
~ 0000efdc: d10103ff sub sp, sp, #0x40 <- 0000dde8(bl)<__vgic_v3_write_apxrn>,0000de50(bl)<__vgic_v3_write_apxrn>,0000deb8(bl)<__vgic_v3_write_apxrn>,0000df20(bl)<__vgic_v3_write_apxrn>
~ 0000efe0: a9037bfd stp x29, x30, [sp, #48]
0000efdc CFA:r31 r29:u r30:u
~ 0000efe4: 9100c3fd add x29, sp, #0x30
~ 0000efe8: f9000fe0 str x0, [sp, #24]
~ 0000efec: b90017e1 str w1, [sp, #20]
~ 0000eff0: b90013e2 str w2, [sp, #16]
__vgic_v3_write_apxrn:842.25 (vgic-v3-sr.c) SbePe u32 val = vcpu_get_reg(║vcpu, rt);
~ 0000eff4: f9400fe8 ldr x8, [sp, #24]
__vgic_v3_write_apxrn:842.31 (vgic-v3-sr.c) sbepe u32 val = vcpu_get_reg(vcpu, ║rt);
~ 0000eff8: b94017e9 ldr w9, [sp, #20]
~ 0000effc: f81f83a8 stur x8, [x29, #-8]
~ 0000f000: 381f43a9 sturb w9, [x29, #-12]
s: 0xf004 0xf03c vcpu_get_reg inlined from __vgic_v3_write_apxrn:842 (vgic-v3-sr.c) <a9b28>:
s vcpu_get_reg:166.10 (kvm_emulate.h) Sbepe return (║reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
+vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xf004 0xf03c (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
+reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xf004 0xf03c (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
~s 0000f004: 385f43a9 ldurb w9, [x29, #-12]
s vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~s 0000f008: 71007d29 subs w9, w9, #0x1f
~s ┌──0000f00c: 540000a1 b.ne f020 <__vgic_v3_write_apxrn+0x44> // b.any
│
~s │┌─0000f010: 14000001 b f014 <__vgic_v3_write_apxrn+0x38> <- 0000f00c(b.cc-succ)<fallthrough>
││
~s │└>0000f014: aa1f03e0 mov x0, xzr <- 0000f010(b)<__vgic_v3_write_apxrn+0x38>
~s │ 0000f018: f90003e0 str x0, [sp]
s │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~s ┌┼──0000f01c: 14000008 b f03c <__vgic_v3_write_apxrn+0x60>
││
s ││ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~s │└─>0000f020: f85f83a8 ldur x8, [x29, #-8] <- 0000f00c(b.cc)<__vgic_v3_write_apxrn+0x44>
s │ vcpu_get_reg:166.56 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[║reg_num];
~s │ 0000f024: 385f43a9 ldurb w9, [x29, #-12]
~s │ 0000f028: 2a0903ea mov w10, w9
s │ vcpu_get_reg:166.31 (kvm_emulate.h) sbepe return (reg_num == 31) ? 0 : ║vcpu_gp_regs(vcpu)->regs[reg_num];
~s │ 0000f02c: 8b0a0d08 add x8, x8, x10, lsl #3
~s │ 0000f030: f940b108 ldr x8, [x8, #352]
~s │ 0000f034: f90003e8 str x8, [sp]
s │ vcpu_get_reg:166.9 (kvm_emulate.h) sbepe return ║(reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
~s │ ┌─0000f038: 14000001 b f03c <__vgic_v3_write_apxrn+0x60>
-vcpu param pointer(const(struct kvm_vcpu<99433>/<9a302>)) 0xf004 0xf03c (DW_OP_fbreg -0x8) vcpu_get_reg(inlined):__vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
-reg_num param typedef(u8=typedef(__u8=unsigned char (base type, DW_ATE_unsigned_char size:1))) 0xf004 0xf03c (DW_OP_fbreg -0xc) vcpu_get_reg(inlined):__vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c
│ │
~ └>└>0000f03c: f94003e0 ldr x0, [sp] <- 0000f01c(b)<__vgic_v3_write_apxrn+0x60>,0000f038(b)<__vgic_v3_write_apxrn+0x60>
__vgic_v3_write_apxrn:842.6 (vgic-v3-sr.c) Sbepe u32 ║val = vcpu_get_reg(vcpu, rt);
~ 0000f040: b9000fe0 str w0, [sp, #12]
__vgic_v3_write_apxrn:844.27 (vgic-v3-sr.c) Sbepe if (!__vgic_v3_get_group(║vcpu))
~ 0000f044: f9400fe0 ldr x0, [sp, #24]
__vgic_v3_write_apxrn:844.7 (vgic-v3-sr.c) sbepe if (!║__vgic_v3_get_group(vcpu))
~ 0000f048: 97fffdc4 bl e758 <__vgic_v3_get_group>
__vgic_v3_write_apxrn:844.6 (vgic-v3-sr.c) sbepe if (║!__vgic_v3_get_group(vcpu))
~ ┌──0000f04c: 350000c0 cbnz w0, f064 <__vgic_v3_write_apxrn+0x88> <- 0000f048(bl-succ)<return>
│
~ │┌─0000f050: 14000001 b f054 <__vgic_v3_write_apxrn+0x78> <- 0000f04c(b.cc-succ)<fallthrough>
││
││ __vgic_v3_write_apxrn:845.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap0rn(║val, n);
~ │└>0000f054: b9400fe0 ldr w0, [sp, #12] <- 0000f050(b)<__vgic_v3_write_apxrn+0x78>
│ __vgic_v3_write_apxrn:845.30 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap0rn(val, ║n);
~ │ 0000f058: b94013e1 ldr w1, [sp, #16]
│ __vgic_v3_write_apxrn:845.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap0rn(val, n);
~ │ 0000f05c: 97fff792 bl cea4 <__vgic_v3_write_ap0rn>
│
~ ┌┼──0000f060: 14000005 b f074 <__vgic_v3_write_apxrn+0x98> <- 0000f05c(bl-succ)<return>
││
││ __vgic_v3_write_apxrn:847.25 (vgic-v3-sr.c) Sbepe __vgic_v3_write_ap1rn(║val, n);
~ │└─>0000f064: b9400fe0 ldr w0, [sp, #12] <- 0000f04c(b.cc)<__vgic_v3_write_apxrn+0x88>
│ __vgic_v3_write_apxrn:847.30 (vgic-v3-sr.c) sbepe __vgic_v3_write_ap1rn(val, ║n);
~ │ 0000f068: b94013e1 ldr w1, [sp, #16]
│ __vgic_v3_write_apxrn:847.3 (vgic-v3-sr.c) sbepe ║__vgic_v3_write_ap1rn(val, n);
~ │ 0000f06c: 97fff7bf bl cf68 <__vgic_v3_write_ap1rn>
│
~ │ ┌─0000f070: 14000001 b f074 <__vgic_v3_write_apxrn+0x98> <- 0000f06c(bl-succ)<return>
│ │
│ │ __vgic_v3_write_apxrn:848.1 (vgic-v3-sr.c) Sbepe ║}
~ └>└>0000f074: a9437bfd ldp x29, x30, [sp, #48] <- 0000f060(b)<__vgic_v3_write_apxrn+0x98>,0000f070(b)<__vgic_v3_write_apxrn+0x98>
~ 0000f078: 910103ff add sp, sp, #0x40
~ 0000f07c: d65f03c0 ret
-vcpu param pointer(struct kvm_vcpu<99433>/<9a302>) 0xefdc 0xf080 (DW_OP_breg31 0x18) __vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:840
-rt param int (base type, DW_ATE_signed size:4) 0xefdc 0xf080 (DW_OP_breg31 0x14) __vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:840
-n param int (base type, DW_ATE_signed size:4) 0xefdc 0xf080 (DW_OP_breg31 0x10) __vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:840
-val var typedef(u32=typedef(__u32=unsigned int (base type, DW_ATE_unsigned size:4))) 0xefdc 0xf080 (DW_OP_breg31 0xc) __vgic_v3_write_apxrn:arch/arm64/kvm/hyp/nvhe/../vgic-v3-sr.c:842
~ 0000f080: d5384028 mrs x8, elr_el1
~ 0000f084: d5384008 mrs x8, spsr_el1
~ 0000f088: d5184008 msr spsr_el1, x8
0000efe8 CFA:r29+16 r29:c-16 r30:c-8
~ 0000f08c: d5184028 msr elr_el1, x8