00001
00037 #include <avr/interrupt.h>
00038 #include <avr/io.h>
00039 #include <avr/wdt.h>
00040 #include <util/delay.h>
00041
00042 #include "scd_hal.h"
00043 #include "scd_io.h"
00044 #include "scd_values.h"
00045 #include "utils.h"
00046
00047 #define DEBUG 1 // Set this to 1 to enable debug code
00048
00049
00050 volatile uint32_t syncCounter;
00051
00052
00053
00054
00063 void EnableTerminalResetInterrupt()
00064 {
00065 EIMSK &= ~(_BV(INT0));
00066 EICRA |= _BV(ISC01);
00067 EICRA &= ~(_BV(ISC00));
00068 EIFR |= _BV(INTF0);
00069 EIMSK |= _BV(INT0);
00070 }
00071
00076 void DisableTerminalResetInterrupt()
00077 {
00078 EIMSK &= ~(_BV(INT0));
00079 }
00080
00088 uint8_t GetTerminalIOLine()
00089 {
00090 return bit_is_set(PINC, PC4);
00091 }
00092
00098 uint8_t GetTerminalResetLine()
00099 {
00100 return bit_is_set(PIND, PD0);
00101 }
00102
00115 void EnableWDT(uint16_t ms)
00116 {
00117 if(ms <= 15)
00118 wdt_enable(WDTO_15MS);
00119 else if(ms <= 30)
00120 wdt_enable(WDTO_30MS);
00121 else if(ms <= 60)
00122 wdt_enable(WDTO_60MS);
00123 else if(ms <= 120)
00124 wdt_enable(WDTO_120MS);
00125 else if(ms <= 250)
00126 wdt_enable(WDTO_250MS);
00127 else if(ms <= 500)
00128 wdt_enable(WDTO_500MS);
00129 else if(ms <= 1000)
00130 wdt_enable(WDTO_1S);
00131 else if(ms <= 2000)
00132 wdt_enable(WDTO_2S);
00133 else if(ms <= 4000)
00134 wdt_enable(WDTO_4S);
00135 else
00136 wdt_enable(WDTO_8S);
00137
00138 WDTCSR |= _BV(WDIE);
00139 }
00140
00144 void DisableWDT()
00145 {
00146 wdt_disable();
00147 WDTCSR &= ~(_BV(WDIE));
00148 }
00149
00153 void ResetWDT()
00154 {
00155 wdt_reset();
00156 }
00157
00167 uint8_t WaitTerminalResetIOLow(uint32_t max_wait)
00168 {
00169 volatile uint8_t tio, treset;
00170 uint8_t result = 0;
00171 uint32_t cnt = 0;
00172
00173 do{
00174 cnt = cnt + 1;
00175 tio = bit_is_clear(PINC, PC4);
00176 treset = bit_is_clear(PIND, PD0);
00177 result = (tio << 1) | treset;
00178
00179 if(max_wait != 0 && cnt == max_wait)
00180 break;
00181 }while(result == 0);
00182
00183 return result;
00184 }
00185
00191 uint16_t GetTerminalFreq()
00192 {
00193 uint8_t sreg;
00194 uint16_t time, result;
00195
00196 sreg = SREG;
00197 cli();
00198 TCNT3 = 1;
00199 asm volatile("nop\n\t"
00200 "nop\n\t"
00201 "nop\n\t"
00202 "nop\n\t"
00203 "nop\n\t"
00204 "nop\n\t"
00205 "nop\n\t"
00206 "nop\n\t"
00207 "nop\n\t"
00208 "nop\n\t"
00209 "nop\n\t"
00210 "nop\n\t"
00211 "nop\n\t"
00212 "nop\n\t"
00213 "nop\n\t"
00214 "nop\n\t"
00215 "nop\n\t"
00216 "nop\n\t"
00217 "nop\n\t"
00218 "nop\n\t"
00219 "nop\n\t"
00220 "nop\n\t"
00221 "nop\n\t"
00222 "nop\n\t"
00223 "nop\n\t"
00224 "nop\n\t"
00225 "nop\n\t"
00226 "nop\n\t"
00227 "nop\n\t"
00228 "nop\n\t"
00229 "nop\n\t"
00230 "nop\n\t"
00231 "nop\n\t"
00232 "nop\n\t"
00233 "nop\n\t"
00234 "nop\n\t"
00235 "nop\n\t"
00236 "nop\n\t"
00237 "nop\n\t"
00238 "nop\n\t"
00239 "nop\n\t"
00240 "nop\n\t"
00241 "nop\n\t"
00242 "nop\n\t"
00243 "nop\n\t"
00244 "nop\n\t"
00245 "nop\n\t"
00246 "nop\n\t"
00247 "nop\n\t"
00248 ::);
00249 time = TCNT3;
00250
00251 if(time == 1)
00252 result = 0;
00253 else
00254 result = (uint16_t)(((F_CPU/1000) * time) / 50);
00255
00256 SREG = sreg;
00257
00258 return result;
00259 }
00260
00268 uint8_t ReadTimerT2()
00269 {
00270 return TCNT2;
00271 }
00272
00273
00281 void StartTimerT2()
00282 {
00283
00284 OCR2A = 16;
00285 TIMSK2 |= _BV(OCIE2A);
00286
00287 TCNT2 = 0;
00288 TCCR2A = _BV(WGM21);
00289 TCCR2B = _BV(CS22) | _BV(CS21) | _BV(CS20);
00290 }
00291
00295 void StopTimerT2()
00296 {
00297 TCCR2B = 0;
00298 TCCR2A = 0;
00299 TIMSK2 = 0;
00300 OCR2A = 0;
00301 }
00302
00310
00311
00312
00313
00314
00321
00322
00323
00324
00325
00331
00332
00333
00334
00335
00339 uint16_t ReadCounterTerminal()
00340 {
00341 uint16_t i;
00342 uint8_t sreg;
00343
00344
00345 sreg = SREG;
00346 cli();
00347 i = TCNT3;
00348 SREG = sreg;
00349
00350 return i;
00351
00352
00353 }
00354
00355
00363 void StartCounterTerminal()
00364 {
00365
00366 TCCR3A = 0x0C;
00367
00368
00369
00370
00371 Write16bitRegister(&OCR3A, ETU_TERMINAL);
00372 TCCR3B = 0x0F;
00373 }
00374
00378 void StopCounterTerminal()
00379 {
00380 TCCR3B = 0;
00381 Write16bitRegister(&TCNT3, 0);
00382 }
00383
00387 void PauseCounterTerminal()
00388 {
00389 TCCR3B = 0;
00390 }
00391
00399 void LoopTerminalETU(uint8_t nEtus)
00400 {
00401 uint8_t i;
00402
00403 Write16bitRegister(&OCR3A, ETU_TERMINAL);
00404 TCCR3A = 0x0C;
00405 Write16bitRegister(&TCNT3, 1);
00406 TIFR3 |= _BV(OCF3A);
00407
00408 for(i = 0; i < nEtus; i++)
00409 {
00410 while(bit_is_clear(TIFR3, OCF3A));
00411 TIFR3 |= _BV(OCF3A);
00412 }
00413 }
00414
00415
00425 void SendByteTerminalNoParity(uint8_t byte, uint8_t inverse_convention)
00426 {
00427 uint8_t bitval, i, parity;
00428 volatile uint8_t tmp;
00429
00430
00431
00432 if(!GetTerminalFreq())
00433 return;
00434
00435
00436
00437 TCCR3A = 0x0C;
00438
00439 PORTC |= _BV(PC4);
00440 DDRC |= _BV(PC4);
00441 Write16bitRegister(&OCR3A, ETU_TERMINAL);
00442 Write16bitRegister(&TCNT3, 1);
00443 TIFR3 |= _BV(OCF3A);
00444
00445
00446
00447
00448
00449 TCCR3A = 0x08;
00450
00451
00452
00453 if(inverse_convention)
00454 {
00455 tmp = ~byte;
00456 byte = 0;
00457 for(i = 0; i < 8; i++)
00458 {
00459 bitval = tmp & _BV((7-i));
00460 if(bitval) byte = byte | _BV(i);
00461 }
00462 }
00463
00464
00465 while(bit_is_clear(TIFR3, OCF3A));
00466 TIFR3 |= _BV(OCF3A);
00467
00468
00469 parity = 0;
00470 for(i = 0; i < 8; i++)
00471 {
00472 bitval = (uint8_t) (byte & (uint8_t)(1 << i));
00473
00474 if(bitval != 0)
00475 {
00476 TCCR3A = 0x0C;
00477 if(!inverse_convention) parity = parity ^ 1;
00478 }
00479 else
00480 {
00481 TCCR3A = 0x08;
00482 if(inverse_convention) parity = parity ^ 1;
00483 }
00484
00485 while(bit_is_clear(TIFR3, OCF3A));
00486 TIFR3 |= _BV(OCF3A);
00487 }
00488
00489
00490 if((!inverse_convention && parity != 0) ||
00491 (inverse_convention && parity == 0))
00492 TCCR3A = 0x0C;
00493 else
00494 TCCR3A = 0x08;
00495
00496
00497
00498 while(bit_is_clear(TIFR3, OCF3A));
00499 TIFR3 |= _BV(OCF3A);
00500 while(bit_is_clear(TIFR3, OCF3A));
00501 TIFR3 |= _BV(OCF3A);
00502
00503
00504 TCCR3A = 0x0C;
00505 DDRC &= ~(_BV(PC4));
00506 PORTC |= _BV(PC4);
00507 }
00508
00519 uint8_t SendByteTerminalParity(uint8_t byte, uint8_t inverse_convention)
00520 {
00521 uint8_t i;
00522 volatile uint8_t tmp;
00523
00524 SendByteTerminalNoParity(byte, inverse_convention);
00525
00526
00527 LoopTerminalETU(1);
00528
00529
00530 if(bit_is_clear(PINC, PC4))
00531 {
00532 Write16bitRegister(&OCR3A, ETU_TERMINAL);
00533 Write16bitRegister(&TCNT3, 1);
00534 TIFR3 |= _BV(OCF3A);
00535 TCCR3A = 0x0C;
00536 i = 0;
00537
00538 do{
00539 i++;
00540
00541
00542 LoopTerminalETU(2);
00543
00544 SendByteTerminalNoParity(byte, inverse_convention);
00545
00546
00547 LoopTerminalETU(1);
00548 tmp = bit_is_clear(PINC, PC4);
00549 }while(i<4 && tmp != 0);
00550
00551 if(tmp != 0)
00552 return 1;
00553 }
00554
00555 return 0;
00556 }
00557
00564 uint8_t WaitForTerminalData(uint16_t max_cycles)
00565 {
00566 uint8_t result = 0;
00567 uint16_t c = 0;
00568 volatile uint8_t bit;
00569
00570 do{
00571 bit = bit_is_set(PINC, PC4);
00572 c = c + 1;
00573
00574 if(max_cycles != 0 && c == max_cycles) break;
00575 }while(bit != 0);
00576
00577
00578 if(bit != 0) result = 1;
00579
00580 return result;
00581 }
00582
00583
00599 uint8_t GetByteTerminalNoParity(
00600 uint8_t inverse_convention,
00601 uint8_t *r_byte,
00602 uint32_t max_wait)
00603 {
00604 volatile uint8_t bit;
00605 volatile uint8_t tio, treset;
00606 uint8_t i, byte, parity;
00607 uint32_t cnt;
00608
00609 TCCR3A = 0x0C;
00610 DDRC &= ~(_BV(PC4));
00611 PORTC |= _BV(PC4);
00612
00613
00614 cnt = 0;
00615 while(1)
00616 {
00617 cnt = cnt + 1;
00618
00619
00620 tio = bit_is_clear(PINC, PC4);
00621 if(tio)
00622 break;
00623
00624
00625 treset = bit_is_clear(PIND, PD0);
00626 if(treset)
00627 return RET_TERMINAL_RESET_LOW;
00628
00629 if(max_wait != 0 && cnt == max_wait)
00630 return RET_TERMINAL_TIME_OUT;
00631 }
00632
00633 Write16bitRegister(&TCNT3, 1);
00634 Write16bitRegister(&OCR3A, ETU_HALF(ETU_TERMINAL));
00635 TIFR3 |= _BV(OCF3A);
00636
00637 while(bit_is_clear(TIFR3, OCF3A));
00638 TIFR3 |= _BV(OCF3A);
00639
00640
00641 bit = bit_is_set(PINC, PC4);
00642 Write16bitRegister(&OCR3A, ETU_TERMINAL);
00643 *r_byte = 0;
00644 byte = 0;
00645 parity = 0;
00646 if(bit) return 1;
00647
00648
00649 for(i = 0; i < 8; i++)
00650 {
00651 while(bit_is_clear(TIFR3, OCF3A));
00652 TIFR3 |= _BV(OCF3A);
00653 bit = bit_is_set(PINC, PC4);
00654
00655 if(inverse_convention && bit == 0)
00656 {
00657 byte = byte | _BV(7-i);
00658 parity = parity ^ 1;
00659 }
00660 else if(inverse_convention == 0 && bit != 0)
00661 {
00662 byte = byte | _BV(i);
00663 parity = parity ^ 1;
00664 }
00665 }
00666
00667 *r_byte = byte;
00668
00669
00670 while(bit_is_clear(TIFR3, OCF3A));
00671 TIFR3 |= _BV(OCF3A);
00672 bit = bit_is_set(PINC, PC4);
00673
00674
00675
00676 Write16bitRegister(&OCR3A, ETU_HALF(ETU_TERMINAL));
00677 while(bit_is_clear(TIFR3, OCF3A));
00678 TIFR3 |= _BV(OCF3A);
00679
00680 if(inverse_convention)
00681 {
00682 if(parity && bit) return 1;
00683 if(!parity && !bit) return 1;
00684 }
00685 else
00686 {
00687 if(parity && !bit) return 1;
00688 if(!parity && bit) return 1;
00689 }
00690
00691 return 0;
00692 }
00693
00708 uint8_t GetByteTerminalParity(
00709 uint8_t inverse_convention,
00710 uint8_t *r_byte,
00711 uint32_t max_wait)
00712 {
00713 uint8_t result;
00714
00715 result = GetByteTerminalNoParity(inverse_convention, r_byte, max_wait);
00716 if(result == RET_ERROR)
00717 {
00718
00719 if(!GetTerminalFreq())
00720 return result;
00721
00722
00723 TCCR3A = 0x0C;
00724 DDRC |= _BV(PC4);
00725
00726 Write16bitRegister(&OCR3A,
00727 ETU_LESS_THAN_HALF(ETU_TERMINAL));
00728 Write16bitRegister(&TCNT3, 1);
00729 TIFR3 |= _BV(OCF3A);
00730
00731 TCCR3A = 0x08;
00732
00733 while(bit_is_clear(TIFR3, OCF3A));
00734 TIFR3 |= _BV(OCF3A);
00735
00736 Write16bitRegister(&OCR3A,
00737 ETU_EXTENDED(ETU_TERMINAL));
00738 while(bit_is_clear(TIFR3, OCF3A));
00739 TIFR3 |= _BV(OCF3A);
00740
00741
00742 TCCR3A = 0x0C;
00743 DDRC &= ~(_BV(PC4));
00744 PORTC |= _BV(PC4);
00745
00746
00747
00748 Write16bitRegister(&OCR3A, ETU_LESS_THAN_HALF(ETU_TERMINAL));
00749 while(bit_is_clear(TIFR3, OCF3A));
00750 TIFR3 |= _BV(OCF3A);
00751 }
00752
00753 return result;
00754 }
00755
00756
00757
00761 uint8_t IsICCInserted()
00762 {
00763 #ifdef INVERT_ICC_SWITCH
00764 return bit_is_clear(PIND, PD1);
00765 #else
00766 return bit_is_set(PIND, PD1);
00767 #endif
00768 }
00769
00770
00774 uint8_t IsICCPowered()
00775 {
00776 return bit_is_clear(PIND, PD7);
00777 }
00778
00784 uint8_t PowerUpICC()
00785 {
00786 if(bit_is_clear(PIND, PD1))
00787 return 1;
00788
00789 PORTD &= ~(_BV(PD7));
00790 DDRD |= _BV(PD7);
00791
00792 return 0;
00793 }
00794
00798 void PowerDownICC()
00799 {
00800 DDRD |= _BV(PD7);
00801 PORTD |= _BV(PD7);
00802 }
00803
00804
00812 void LoopICCETU(uint8_t nEtus)
00813 {
00814 uint8_t i;
00815
00816 Write16bitRegister(&OCR1A, ETU_ICC);
00817 TCCR1A = 0x30;
00818 Write16bitRegister(&TCNT1, 1);
00819 TIFR1 |= _BV(OCF1A);
00820
00821 for(i = 0; i < nEtus; i++)
00822 {
00823 while(bit_is_clear(TIFR1, OCF1A));
00824 TIFR1 |= _BV(OCF1A);
00825 }
00826 }
00827
00835 uint8_t WaitForICCData(uint32_t max_cycles)
00836 {
00837 uint8_t result = 0;
00838 uint32_t c = 0;
00839 volatile uint8_t bit;
00840
00841 do{
00842 bit = bit_is_set(PINB, PB6);
00843 c = c + 1;
00844
00845 if(max_cycles != 0 && c == max_cycles) break;
00846 }while(bit != 0);
00847
00848
00849 if(bit != 0) result = 1;
00850
00851 return result;
00852 }
00853
00864 uint8_t GetByteICCNoParity(uint8_t inverse_convention, uint8_t *r_byte)
00865 {
00866 volatile uint8_t bit;
00867 uint8_t i, byte, parity;
00868
00869 TCCR1A = 0x30;
00870 DDRB &= ~(_BV(PB6));
00871
00872 #if PULL_UP_HIZ_ICC
00873 PORTB |= _BV(PB6);
00874 #else
00875 PORTB &= ~(_BV(PB6));
00876 #endif
00877
00878
00879 while(bit_is_set(PINB, PB6));
00880
00881 Write16bitRegister(&TCNT1, 1);
00882 Write16bitRegister(&OCR1A, ETU_HALF(ETU_ICC));
00883 TIFR1 |= _BV(OCF1A);
00884
00885 while(bit_is_clear(TIFR1, OCF1A));
00886 TIFR1 |= _BV(OCF1A);
00887
00888
00889 bit = bit_is_set(PINB, PB6);
00890 Write16bitRegister(&OCR1A, ETU_ICC);
00891 *r_byte = 0;
00892 byte = 0;
00893 parity = 0;
00894 if(bit) return 1;
00895
00896
00897 for(i = 0; i < 8; i++)
00898 {
00899 while(bit_is_clear(TIFR1, OCF1A));
00900 TIFR1 |= _BV(OCF1A);
00901 bit = bit_is_set(PINB, PB6);
00902
00903 if(inverse_convention && bit == 0)
00904 {
00905 byte = byte | _BV(7-i);
00906 parity = parity ^ 1;
00907 }
00908 else if(inverse_convention == 0 && bit != 0)
00909 {
00910 byte = byte | _BV(i);
00911 parity = parity ^ 1;
00912 }
00913 }
00914
00915 *r_byte = byte;
00916
00917
00918 while(bit_is_clear(TIFR1, OCF1A));
00919 TIFR1 |= _BV(OCF1A);
00920 bit = bit_is_set(PINB, PB6);
00921
00922
00923 Write16bitRegister(&OCR1A, ETU_HALF(ETU_ICC));
00924 while(bit_is_clear(TIFR1, OCF1A));
00925 TIFR1 |= _BV(OCF1A);
00926
00927 if(inverse_convention)
00928 {
00929 if(parity && bit) return 1;
00930 if(!parity && !bit) return 1;
00931 }
00932 else
00933 {
00934 if(parity && !bit) return 1;
00935 if(!parity && bit) return 1;
00936 }
00937
00938 return 0;
00939 }
00940
00941
00952 uint8_t GetByteICCParity(uint8_t inverse_convention, uint8_t *r_byte)
00953 {
00954 uint8_t result;
00955
00956 result = GetByteICCNoParity(inverse_convention, r_byte);
00957 if(result != 0)
00958 {
00959
00960 if(!IsICCInserted())
00961 return result;
00962
00963
00964 TCCR1A = 0x30;
00965 DDRB |= _BV(PB6);
00966 Write16bitRegister(&OCR1A,
00967 ETU_LESS_THAN_HALF(ETU_ICC));
00968 Write16bitRegister(&TCNT1, 1);
00969 TIFR1 |= _BV(OCF1A);
00970 TCCR1A = 0x20;
00971
00972 while(bit_is_clear(TIFR1, OCF1A));
00973 TIFR1 |= _BV(OCF1A);
00974 Write16bitRegister(&OCR1A,
00975 ETU_EXTENDED(ETU_ICC));
00976 while(bit_is_clear(TIFR1, OCF1A));
00977 TIFR1 |= _BV(OCF1A);
00978
00979
00980 TCCR1A = 0x30;
00981 DDRB &= ~(_BV(PB6));
00982 PORTB |= _BV(PB6);
00983
00984
00985 Write16bitRegister(&OCR1A, ETU_LESS_THAN_HALF(ETU_ICC));
00986 while(bit_is_clear(TIFR1, OCF1A));
00987 TIFR1 |= _BV(OCF1A);
00988 }
00989
00990 return result;
00991 }
00992
01001 void SendByteICCNoParity(uint8_t byte, uint8_t inverse_convention)
01002 {
01003 uint8_t bitval, i, parity;
01004 volatile uint8_t tmp;
01005
01006 if(!IsICCInserted())
01007 return;
01008
01009
01010
01011 TCCR1A = 0x30;
01012 PORTB |= _BV(PB6);
01013 DDRB |= _BV(PB6);
01014 Write16bitRegister(&OCR1A, ETU_ICC);
01015 Write16bitRegister(&TCNT1, 1);
01016 TIFR1 |= _BV(OCF1A);
01017
01018
01019
01020
01021
01022 TCCR1A = 0x20;
01023
01024
01025
01026 if(inverse_convention)
01027 {
01028 tmp = ~byte;
01029 byte = 0;
01030 for(i = 0; i < 8; i++)
01031 {
01032 bitval = tmp & _BV((7-i));
01033 if(bitval) byte = byte | _BV(i);
01034 }
01035 }
01036
01037
01038 while(bit_is_clear(TIFR1, OCF1A));
01039 TIFR1 |= _BV(OCF1A);
01040
01041
01042 parity = 0;
01043 for(i = 0; i < 8; i++)
01044 {
01045 bitval = (uint8_t) (byte & (uint8_t)(1 << i));
01046
01047 if(bitval != 0)
01048 {
01049 TCCR1A = 0x30;
01050 if(!inverse_convention) parity = parity ^ 1;
01051 }
01052 else
01053 {
01054 TCCR1A = 0x20;
01055 if(inverse_convention) parity = parity ^ 1;
01056 }
01057
01058 while(bit_is_clear(TIFR1, OCF1A));
01059 TIFR1 |= _BV(OCF1A);
01060 }
01061
01062
01063 if((!inverse_convention && parity != 0) ||
01064 (inverse_convention && parity == 0))
01065 TCCR1A = 0x30;
01066 else
01067 TCCR1A = 0x20;
01068
01069
01070
01071 while(bit_is_clear(TIFR1, OCF1A));
01072 TIFR1 |= _BV(OCF1A);
01073 while(bit_is_clear(TIFR1, OCF1A));
01074 TIFR1 |= _BV(OCF1A);
01075
01076
01077 TCCR1A = 0x30;
01078 DDRB &= ~(_BV(PB6));
01079 PORTB |= _BV(PB6);
01080 }
01081
01092 uint8_t SendByteICCParity(uint8_t byte, uint8_t inverse_convention)
01093 {
01094 uint8_t i;
01095 volatile uint8_t tmp;
01096
01097 SendByteICCNoParity(byte, inverse_convention);
01098
01099
01100 LoopICCETU(1);
01101
01102
01103 if(bit_is_clear(PINB, PB6))
01104 {
01105 Write16bitRegister(&OCR1A, ETU_ICC);
01106 Write16bitRegister(&TCNT1, 1);
01107 TIFR1 |= _BV(OCF1A);
01108 TCCR1A = 0x30;
01109 i = 0;
01110
01111 do{
01112 i++;
01113
01114
01115 LoopICCETU(2);
01116
01117 SendByteICCNoParity(byte, inverse_convention);
01118
01119
01120 LoopICCETU(1);
01121 tmp = bit_is_clear(PINB, PB6);
01122 }while(i<4 && tmp != 0);
01123
01124 if(tmp != 0)
01125 return 1;
01126 }
01127
01128 return 0;
01129 }
01130
01131
01138 void SetICCResetLine(uint8_t high)
01139 {
01140 if(high)
01141 PORTD |= _BV(PD4);
01142 else
01143 PORTD &= ~(_BV(PD4));
01144 }
01145
01153 uint8_t ActivateICC(uint8_t warm)
01154 {
01155 if(warm)
01156 {
01157
01158 PORTD &= ~(_BV(PD4));
01159 DDRD |= _BV(PD4);
01160 }
01161 else{
01162
01163 PORTB &= ~(_BV(PB6));
01164 DDRB |= _BV(PB6);
01165 #if ICC_CLK_OCR0A
01166 PORTB &= ~(_BV(PB7));
01167 DDRB |= _BV(PB7);
01168 #else
01169
01170 PORTB &= ~(_BV(PB7));
01171 DDRB &= ~(_BV(PB7));
01172 #endif
01173 PORTD &= ~(_BV(PD4));
01174 DDRD |= _BV(PD4);
01175 _delay_us(ICC_VCC_DELAY_US);
01176 if(PowerUpICC())
01177 {
01178 DeactivateICC();
01179 return 1;
01180 }
01181 _delay_us(ICC_VCC_DELAY_US);
01182 }
01183
01184
01185 DDRB &= ~(_BV(PB6));
01186 #if PULL_UP_HIZ_ICC
01187 PORTB |= _BV(PB6);
01188 #else
01189 PORTB &= ~(_BV(PB6));
01190 #endif
01191
01192 if(warm == 0)
01193 {
01194
01195
01196
01197 OCR0A = ICC_CLK_OCR0A;
01198 TCNT0 = 0;
01199 #if ICC_CLK_OCR0A
01200 TCCR0A = 0x42;
01201 TCCR0B = 0x01;
01202 #else
01203 TCCR0A = 0;
01204 TCCR0B = 0;
01205 #endif
01206
01207 TCCR1A = 0x30;
01208 Write16bitRegister(&OCR1A, ETU_ICC);
01209 TCCR1B = ICC_CLK_TCCR1B;
01210 TCCR1C = 0x40;
01211
01212 }
01213
01214 return 0;
01215 }
01216
01220 void DeactivateICC()
01221 {
01222
01223 PORTD &= ~(_BV(PD4));
01224 DDRD |= _BV(PD4);
01225
01226
01227 TCCR0A = 0;
01228 TCCR0B = 0;
01229 TCCR1A = 0;
01230 TCCR1B = 0;
01231
01232 #if ICC_CLK_OCR0A
01233
01234 PORTB &= ~(_BV(PB7));
01235 DDRB |= _BV(PB7);
01236 #endif
01237
01238
01239 PORTB &= ~(_BV(PB6));
01240 DDRB |= _BV(PB6);
01241
01242
01243 PORTD |= _BV(PD7);
01244 DDRD |= _BV(PD7);
01245 }
01246
01250 void EnableICCInsertInterrupt()
01251 {
01252 EICRA |= _BV(ISC10);
01253 EICRA &= ~(_BV(ISC11));
01254 EIMSK |= _BV(INT1);
01255 }
01256
01260 void DisableICCInsertInterrupt()
01261 {
01262 EIMSK &= ~(_BV(INT1));
01263 }
01264