Structure of the git repository
The structure of the repository is as follows:
ariane
: The root of the ETHZ riscv system verilog processorariane/bootrom
: The simulation boot romariane/ci
: The check-in checksariane/docs
: The Ariane CPU documentationariane/fpga
: The ETHZ version of the Ariane FPGA build environmentariane/include
: The main Ariane include directoryariane/openpiton
: The multi-CPU L1.5 infrastructure (not used in this project)ariane/scripts
: The build scriptsariane/src
: The majority of the system verilog source filesariane/tb
: The example files to use Ariane in a testbenchbuildroot-2019.11.1-lowrisc
: The modified buildroot installationbuildroot-2019.11.1-lowrisc/arch
: The architecture specific filesbuildroot-2019.11.1-lowrisc/board
: The board specific filesbuildroot-2019.11.1-lowrisc/boot
: The boot-loader filesbuildroot-2019.11.1-lowrisc/configs
: The configuration filesbuildroot-2019.11.1-lowrisc/dl
: The staging area for downloadsbuildroot-2019.11.1-lowrisc/docs
: The buildroot documentationbuildroot-2019.11.1-lowrisc/fs
: The staging area for the root file systembuildroot-2019.11.1-lowrisc/linux
: The linux supportbuildroot-2019.11.1-lowrisc/mainfs
: The majority of packages are built herebuildroot-2019.11.1-lowrisc/package
: The patches and package build instructionsbuildroot-2019.11.1-lowrisc/rescuefs
: The mini root rescue filing systembuildroot-2019.11.1-lowrisc/support
: The support filesbuildroot-2019.11.1-lowrisc/system
: The system filesbuildroot-2019.11.1-lowrisc/toolchain
: The compiler filesbuildroot-2019.11.1-lowrisc/utils
: The utility filesbuildroot-fs-overlay
: The main overlay (replacement root file system files)buildroot-fs-overlay/etc
: The /etc overlaybuildroot-fs-overlay/usr
: The /usr /overlaybuildroot-fs-overlay/var
: The /var overlaybuildroot-rescue-overlay
: The rescue mini root overlaybuildroot-rescue-overlay/etc
: The rescue /etc overlaydebian-riscv64
: The optional debian operating system installation scriptsdebian-riscv64/work
: The scripts and miscellaneous files for the Debian install.fpga
: The lowrisc primary FPGA specific source and scriptsfpga/constraints
: The timing and pin constraintsfpga/genesys2_ariane
: The auto-generated GenesysII Ariane variantfpga/genesys2_rocket
: The auto-generated GenesysII Rocket variantfpga/nexys4_ddr_ariane
: The auto-generated Nexys4-DDR Ariane variantfpga/nexys4_ddr_rocket
: The auto-generated Nexys4-DDR Rocket variantfpga/reports
: The FPGA timing and area reportsfpga/scripts
: The build scriptsfpga/src
: The main lowrisc verilog/system verilog source codeapb_uart
: UART implementation intended to be software compatible with ns16750spi_mem_programmer
: Simple implementation of a QSPI memory interfaceariane-ethernet
: Ethernet module adapted for 1000BaseT
fpga/work-fpga
: The auto-generated results and bitstream areafpga/xilinx
: The Xilinx FPGA IP generation scripts and resultsjenkins
: The jenkins regression scripts directory (obsolete)lowrisc-quickstart
: The staging area for binary installsrocket-chip
: The root of the Berkeley Rocket CPU writen in Chiselrocket-chip/bootrom
: The first-stage boot and device tree sourcerocket-chip/chisel3
: The Chisel language filesrocket-chip/csrc
: The C source filesrocket-chip/emulator
: The simulation filesrocket-chip/firrtl
: The FIR intermediate representation register transfer languagerocket-chip/hardfloat
: The hardware floating point support filesrocket-chip/lib
: The library directoryrocket-chip/macros
: The macros directoryrocket-chip/project
: The project directoryrocket-chip/regression
: The regression testsrocket-chip/scripts
: The build scriptsrocket-chip/src
: The toplevel source directoryrocket-chip/target
: The toplevel target directoryrocket-chip/torture
: The torture testsrocket-chip/vsim
: The Verilog simulation directoryrocket-chip/vsrc
: The Verilog hand-written source filesscripts
: The top-level scripts (obsolete)scripts/debug_rom
: The debug methodology (obsolete)src
: The toplevel source directorysrc/OpenIP
: The AXI infrastructure written by Gary Guosrc/test
: The testbench source code in behavioural Verilog
Ensure you have all the necessary packages installed:
sudo apt-get install autoconf automake autotools-dev curl \
libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison \
flex texinfo gperf libncurses5-dev libusb-1.0-0-dev libboost-dev \
swig git libtool libreadline-dev libelf-dev python-dev \
microcom chrpath gawk texinfo nfs-kernel-server xinetd pseudo \
libusb-1.0-0-dev hugo device-tree-compiler zlib1g-dev libssl-dev \
debootstrap debian-ports-archive-keyring qemu-user-static iverilog \
openjdk-8-jdk-headless iperf3 libglib2.0-dev libpixman-1-dev
Download the code
The code is hosted in the
lowRISC chip git repository. All
external repositories are fetched as submodules, apart from the linux-kernel
which is created from upstream sources and a patch set. In case you want to work on multiple branches,
give each checkout a unique name (such as lowrisc-chip-ariane-v0.7)
You need to clone the proper branch (ariane-v0.7
):
git clone -b ariane-v0.7 --recursive https://github.com/lowrisc/lowrisc-chip.git lowrisc-chip-ariane-v0.7
cd lowrisc-chip-ariane-v0.7
Submodules that did not need to be modified for this release are hosted in the original repository, but the version will be frozen at the version that was tested by us, which probably will not be the latest.
Next steps: