ARM Project Week 1

Frank Stajano (fms27)

2004-05-13

University of Cambridge
Department of Engineering
Laboratory for Communication Engineering

Project matched what you expected/hoped from the description
No )-:
 |-:
 |-:*
 |-:*****
Yes (-:**************
 
Contents
Boring )-:
 |-:
 |-:*
 |-:*****
Interesting (-:**************
 
Pace
Too slow )-:
 |-:***
Just right (-:**************
 |-:***
Too fast )-:
 
Difficulty
Too easy )-:
 |-:**
Just right (-:**************
 |-:****
Too hard )-:
 
Examples
Too many )-:
 |-:
Just right (-:*************
 |-:*******
Too few )-:
 
You are learning useful skills
No )-:
 |-:
 |-:
 |-:***
Yes (-:*****************
 
Project web site
Useless )-:
 |-:
 |-:
 |-:****
Useful (-:****************
 
Project web site
Too terse )-:
 |-:
Just right (-:**************
 |-:****
Too verbose )-:*
 
Explanations from project leader
Obscure )-:
 |-:**
 |-:**
 |-:********
Illuminating (-:********
 
Explanations from project leader
Superficial )-:
 |-:****
 |-:*****
 |-:********
Exhaustive (-:***
 
Explanations from project leader
Too rare )-:
 |-:*****
Just right (-:**************
 |-:*
Too frequent )-:
 
Individual help from demonstrators and leader
Obscure )-:
 |-:
 |-:**
 |-:********
Illuminating (-:*********
 
Individual help from demonstrators and leader
Long wait )-:*
 |-:*****
 |-:******
 |-:*****
Instant response (-:**
 
How do you feel about having chosen this project?
Sad )-:
 |-:
 |-:
 |-:****
Happy (-:****************
 

Positive comments:

Good project

Very fun!

Challenging and rewarding. Offers sufficient scope to personal investigation that it makes the project highly addictive and absorbing.

Very interesting work, girlfriend will be impressed.

Tasks are v interesting.

Negative comments:

Very poor compiler which often corrupts .acf's in use...

Would help if the ARM presentation were done sooner, making it easier to start week 2's work before week 2...

The software is frustrating and slow - but I guess you already know this!

Terrible Verilog software! I think I could connect gates together quicker than it compiles!

It would be helpful if the students were provided with a handbook of Verilog and ARM Assembler 'User guide' (something like the one for MATLAB). There should be a session between the first day and the last day (e.g. on Wednesday) - probably optional - for solving some questions or problems that the students may have.

Two demonstrators gave me wrong advice regarding the optimal design of a PRNG.

Some earlier info on ARM itself would be helpful for people wanting to get started on week 2's stuff once week 1's is finished.

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