RANKING COST: ONE-STAGE CIRCUIT ROUTING BY DIRECTLY OPTIMIZING GLOBAL OBJECTIVE FUNC-TION

Abstract

Circuit routing has been a historically challenging problem in designing electronic systems such as very large-scale integration (VLSI) and printed circuit boards (PCBs). The main challenge is that connecting a large number of electronic components under specific design rules and constraints involves a very large search space, which is proved to be NP-complete. Early solutions are typically designed with hard-coded heuristics, which suffer from problems of non-optimal solutions and lack of flexibility for new design needs. Although a few learning-based methods have been proposed recently, their methods are cumbersome and hard to extend to large-scale applications. In this work, we propose a new algorithm for circuit routing, named as Ranking Cost (RC), which innovatively combines searchbased methods (i.e., A* algorithm) and learning-based methods (i.e., Evolution Strategies) to form an efficient and trainable router under a proper parameterization. Different from two-stage routing methods ( i.e., first global routing and then detailed routing), our method involves an one-stage procedure that directly optimizes the global objective function, thus it can be easy to adapt to new routing rules and constraints. In our method, we introduce a new set of variables called cost maps, which can help the A* router to find out proper paths to achieve the global objective. We also train a ranking parameter, which can produce the ranking order and further improve the performance of our method. Our algorithm is trained in an end-to-end manner and does not use any artificial data or human demonstration. In the experiments, we compare with the sequential A* algorithm and a canonical reinforcement learning approach, and results show that our method outperforms these baselines with higher connectivity rates and better scalability. Our ablation study shows that our trained cost maps can capture the global information and guide the routing result to approach global optima.

1. INTRODUCTION

As described in Moore's Law (Schaller, 1997) , the number of transistors in a dense integrated circuit (IC) increases exponentially over time and the complexity of chips and printed circuit boards (PCBs) becomes higher and higher. Such high complexity makes the IC design a time-consuming and errorprone work. Thus more capable automatic design systems, such as electronic design automation (EDA) tools, are needed to improve the performance. In the flow of IC designs, we need to find proper paths to place wires which connect electronic components on ICs, and these wires need to achieve expected connectivity under certain constraints. One of the most important constraints is that wires on the same layout should not intersect. In addition, to reduce the signal propagation delay, the wire-length should be minimized. This is a critical and challenging stage in the IC design flow (Hu & Sapatnekar, 2001) , known as circuit routing, which has been studied by lots of researchers (Kramer, 1984; Zhang & Chu, 2012; He & Bao, 2020) . Circuit routing involves a large number of nets (a net is a set of vertices with the same electrical property) to be routed, which is computationally expensive and makes manual design extremely time-consuming (Kong et al., 2009; Coombs & Holden, 2001) . Even under the simplest setting, where only two pairs of pins need to be routed, it is an NP-complete problem (Kramer, 1984) . Although lots of circuit routing algorithms have been proposed (Zhang, 2016) , there still remain three major challenges: (1) Early solutions (Hu & Sapatnekar, 2001) are typically designed with hard-coded heuristics , which suffer from problems of non-optimal solutions (Zhang, 2016) and lack of flexibility over new design needs. Therefore, a more powerful routing method that does not depend on domain knowledge is highly desired. (2) To reduce the difficulty of complex routing problems, traditional routing algorithms often adopt a two-stage procedure -first global routing and then detailed routing (Chen & Chang, 2009; Kahng et al., 2011) . The problem is that these two stages do not always coordinate well (Zhang & Chu, 2012; Shi & Davoodi, 2017) . Sometimes a low-congested global routing result may lead to downstream detailed router un-routable. Hence, an end-to-end algorithm is preferred which can optimize the final global objective (e.g., the total wire-length) directly. (3) Although a few learning-based methods have been proposed (Liao et al., 2020; He & Bao, 2020) recently, their methods are hard to extend to large-scale applications. In real settings, there are lots of components and nets on a single chip, which shows greater demand for the scalability of routing algorithms. To relieve the problems mentioned above, we propose a new algorithm, denoted as Ranking Cost (RC), for circuit routing. In this paper, we innovatively combine search-based methods (i.e., A* algorithm) and learning-based methods (i.e., Evolution Strategies (Salimans et al., 2017) ) to form an trainable router with proper parametrization. Our method is flexible for integrating new constraints and rules so long as they can be merged into the global objective function. Moreover, our method is an one-stage algorithm, which optimizes the global objective function directly. In our method, we introduce a new set of variables called cost maps, which can help the A* routers to find out proper paths to achieve the global objective. We also train a ranking parameter, which can produce the ranking order and further improve the performance of our method. In the experiments, we compare our method with the commonly used A* method and a canonical reinforcement learning approach, and results show that our method outperforms these baselines with higher connectivity rates. Our ablation study also shows that trained cost maps can capture the global information and guide the routing solution to approach global optimal. Experiments also show that our method is scalable to larger applications.

2. RELATED WORK

In this section, we summarize the related work on circuit routing.

2.1. TWO-STAGE ROUTING ALGORITHMS

The routing problem can be heuristically separated into two stages, the first being the global routing step, followed by detailed routing. On the one hand, there are multiple heuristic-based approaches for global routing including regionwise routing (Hu & Sapatnekar, 2001) , force-directed routing (Mo et al., 2001) , and rip-up and reroute (Cho et al., 2007) . On the other hand, the most commonly used detailed routing algorithms are channel routing and its variants (Ho et al., 1991; Mandal et al., 2020) , which decompose the routing region into routing channels and generate wires in these channels (Chen & Chang, 2009) . One main issue of the two-stage methods is that these two stages do not always coordinate well (Shi & Davoodi, 2017) , which results in enormous difficulty in joint optimization. Instead, our method is an one-stage algorithm and new design constraints can be simply involved into the objective function without changing the algorithm itself.

2.2. SEQUENTIAL ROUTING ALGORITHMS

A more straightforward strategy for circuit routing is to select a specific order and then route nets sequentially, e.g., sequential A* algorithm and Lees algorithm (Huang et al., 2014; Malavasi & Sangiovanni-Vincentelli, 1993) . The major advantage of this type of approaches is that the congestion information for previously routed nets can be taken into consideration while routing the current one. However, the drawback of these sequential approaches is that the quality of the solution is very sensitive to the orders (Zhang, 2016) . Moreover, earlier routed paths only focus on finding their own best solutions and are impossible to take into account the situation of subsequent paths. Such greedy strategies may make a solvable circuit routing problem insolvable. Figure 1 shows an example that the sequential A* algorithm will fail to handle. In this example, there are two pairs of points to be routed, i.e., we should connect start vertices S i and end vertices E i , i ∈ {1, 2}, respectively. If we

