// CBG Orangepath HPR L/S System

// Verilog output file generated at 14/05/2019 21:04:41
// CBG-BSV TOY COMPILER VERSION 0.40 ALPHA  1st-May-2019
//  /home/djg11/d320/hprls/bsvc/priv_distro/lib/bsv.exe -report-each-step -incdir=/home/djg11/d320/hprls/bsvc/priv_distro/libs/camlib -vnl=dut.v -give-backtrace -o dut.v smalltests/Test1f.bsv -bsv-enable-multiple-writes=enable -bsv-scheduler=none
`timescale 1ns/1ns


module dut(/* portgroup= abstractionName=L2590-vg pi_name=net2batchdirectoratenets10 */
input CLK, input RST_N);

function [9:0] rtl_unsigned_bitextract1;
   input [31:0] arg;
   rtl_unsigned_bitextract1 = $unsigned(arg[9:0]);
   endfunction


function [9:0] rtl_unsigned_bitextract0;
   input [31:0] arg;
   rtl_unsigned_bitextract0 = $unsigned(arg[9:0]);
   endfunction

// abstractionName=nokind
  reg [9:0] Test1f_mkTest1f_shandy_read_RV;
  reg Test1f_mkTest1f_shandy_write_EN;
  reg [9:0] Test1f_mkTest1f_shandy_write_din;
  wire Test1f_mkTest1f_shower_FIRE;
  reg Test1f_mkTest1f_test_1f_inc3_FIRE;
  wire Test1f_mkTest1f_test_1f_inc1_FIRE;
// abstractionName=share-nets pi_name=shareAnets10
  wire [9:0] hprpin500042x10;
 always   @(posedge CLK )  begin 
      //Start structure cvtToVerilogTest1f.mkTest1f/1.0
      if (!RST_N)  Test1f_mkTest1f_shandy_read_RV <= 32'd30;
           else  begin 
              if (Test1f_mkTest1f_shower_FIRE) $display("Shandy is %1d", rtl_unsigned_bitextract0(10'd3+rtl_unsigned_bitextract1(10'd1
                  +Test1f_mkTest1f_shandy_read_RV)));
                  if (Test1f_mkTest1f_shandy_write_EN)  Test1f_mkTest1f_shandy_read_RV <= Test1f_mkTest1f_shandy_write_din;
                   end 
              //End structure cvtToVerilogTest1f.mkTest1f/1.0


       end 
      

assign Test1f_mkTest1f_shower_FIRE = 32'd1;

always @(*) Test1f_mkTest1f_test_1f_inc3_FIRE = (32'h0/*0:USA10*/==rtl_unsigned_bitextract0((rtl_unsigned_bitextract1(10'd1+Test1f_mkTest1f_shandy_read_RV)%32'sd5)));

assign Test1f_mkTest1f_test_1f_inc1_FIRE = 32'd1;

always @(*) Test1f_mkTest1f_shandy_write_EN = Test1f_mkTest1f_test_1f_inc1_FIRE || Test1f_mkTest1f_test_1f_inc3_FIRE && (32'h0/*0:USA10*/==rtl_unsigned_bitextract0((rtl_unsigned_bitextract1(10'd1
+Test1f_mkTest1f_shandy_read_RV)%32'sd5)));

always @(*) Test1f_mkTest1f_shandy_write_din = hprpin500042x10;

assign hprpin500042x10 = (Test1f_mkTest1f_test_1f_inc3_FIRE && (32'h0/*0:USA10*/==rtl_unsigned_bitextract0((rtl_unsigned_bitextract1(10'd1+Test1f_mkTest1f_shandy_read_RV
)%32'sd5)))? rtl_unsigned_bitextract0(10'd3+rtl_unsigned_bitextract1(10'd1+Test1f_mkTest1f_shandy_read_RV)): rtl_unsigned_bitextract1(10'd1
+Test1f_mkTest1f_shandy_read_RV));

// Structural Resource (FU) inventory for dut:// 2 vectors of width 1
// 2 vectors of width 10
// Total state bits in module = 22 bits.
// 12 continuously assigned (wire/non-state) bits 
// Total number of leaf cells = 0
endmodule