// CBG Orangepath HPR L/S System

// Verilog output file generated at 14/05/2019 21:56:59
// CBG-BSV TOY COMPILER VERSION 0.40 ALPHA  1st-May-2019
//  /home/djg11/d320/hprls/bsvc/priv_distro/lib/bsv.exe -report-each-step -incdir=/home/djg11/d320/hprls/bsvc/priv_distro/libs/camlib -vnl=dut.v -give-backtrace -o dut.v smalltests/Test1i.bsv -bsv-round-robin=enable
`timescale 1ns/1ns


module dut(/* portgroup= abstractionName=nokind */
/* portgroup= abstractionName=L2590-vg pi_name=net2batchdirectoratenets10 */
input CLK, input RST_N);

function [31:0] rtl_unsigned_extend0;
   input argbit;
   rtl_unsigned_extend0 = { 31'b0, argbit };
   endfunction

// abstractionName=nokind
  reg [31:0] Test1i_mkTest1iBench_fbar_orderDrink_no;
  reg [31:0] Test1i_mkTest1iBench_fbar_orderDrink_which;
  reg Test1i_mkTest1iBench_fbar_orderDrink_EN;
  wire Test1i_mkTest1iBench_fbar_orderDrink_RDY;
  reg Test1i_mkTest1iBench_drinkWine_FIRE;
  reg Test1i_mkTest1iBench_drinkBeer_FIRE;
  reg ARXshedtree1_10;
  reg ARXshedtree1_10_advance;
 always   @(posedge CLK )  begin 
      //Start structure cvtToVerilogTest1i.mkTest1iBench/1.0
      if (!RST_N)  ARXshedtree1_10 <= 32'd0;
           else if (ARXshedtree1_10_advance)  ARXshedtree1_10 <= ((32'd1+rtl_unsigned_extend0(ARXshedtree1_10))%32'd2);
              //End structure cvtToVerilogTest1i.mkTest1iBench/1.0


       end 
      

  Test1i_mkBarTender Test1i_mkTest1iBench_fbar(
        .Test1i_mkBarTender_orderDrink_RDY(Test1i_mkTest1iBench_fbar_orderDrink_RDY),
        .Test1i_mkBarTender_orderDrink_EN(Test1i_mkTest1iBench_fbar_orderDrink_EN
),
        .Test1i_mkBarTender_orderDrink_which(Test1i_mkTest1iBench_fbar_orderDrink_which),
        .Test1i_mkBarTender_orderDrink_no(Test1i_mkTest1iBench_fbar_orderDrink_no
),
        .CLK(CLK),
        .RST_N(RST_N));
always @(*) Test1i_mkTest1iBench_drinkBeer_FIRE = RST_N && Test1i_mkTest1iBench_fbar_orderDrink_RDY && (32'sd0==ARXshedtree1_10);

always @(*) Test1i_mkTest1iBench_drinkWine_FIRE = RST_N && Test1i_mkTest1iBench_fbar_orderDrink_RDY && (32'h1/*1:AUTB12*/==ARXshedtree1_10);

always @(*) ARXshedtree1_10_advance = RST_N && Test1i_mkTest1iBench_fbar_orderDrink_RDY;

always @(*) Test1i_mkTest1iBench_fbar_orderDrink_EN = Test1i_mkTest1iBench_drinkBeer_FIRE || Test1i_mkTest1iBench_drinkWine_FIRE;

always @(*) Test1i_mkTest1iBench_fbar_orderDrink_which = (Test1i_mkTest1iBench_drinkWine_FIRE? 32'd2: 32'd1);

always @(*) Test1i_mkTest1iBench_fbar_orderDrink_no = (Test1i_mkTest1iBench_drinkWine_FIRE? 32'd10: 32'd2);

// Structural Resource (FU) inventory for dut:// 5 vectors of width 1
// 2 vectors of width 32
// Total state bits in module = 69 bits.
// 1 continuously assigned (wire/non-state) bits 
//   cell Test1i_mkBarTender count=1
// Total number of leaf cells = 1
endmodule