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Arrays and RAM Inference in RTL

RTL languages support bits, bit vectors (words) and arrays of bit vectors (RAMs). Arrays in the RTL can be synthesised to structural instances of RAM memories or else to register files made of flip flops. Certain patterns of array use are defined to trigger RAM inference, where a RAM is instantiated in the net list.

RAM inference is supported in FPGA logic synthesis tools. ASIC synthesis tools require the use of the alternativ, which is for the RTL to contain explicit structural instances.

    reg [31:0] myram [32767:0];  // 32K words of 32 bits each.
    // To execute the following in one clock cycle needs two RAM ports
    always @(posedge clk) myram[a] <= myram[b] + 2;

Even when RAM inference is available, it is sometimes easiest to write a leaf module that behaves like the RAM and then structurally instantiate that in the main RTL. The RAM inference will then just act inside the leaf module and edits to the main RTL cannot violate the pattern that triggers the inference procedure.

The pattern needed to trigger RAM inference is nothing more than an RTL model of the real RAM. This example is for a dual-ported (one read, one write) SRAM. SRAM is synchronous RAM with a read latency. Here the latency is one cycle.

  module R1W1RAM(din, waddr, clk, wen, raddr, dout);   // This is both a behavioural model
    input clk, wen;                                    // of the SRAM and a pattern that
    input [14:0] waddr, raddr;                         // should trigger RAM inference in
    input [31:0] din;                                  // FPGA tools.
    output [31:0] dout; 

    reg [31:0] myram [32767:0];          // 32K words of 32 bits each.
    always @(posedge clk) begin       
         dout <= myram[raddr];           // Data out is registered once without otherwise being
         if (wen) myram[waddr] <= din;   // looked at. Write data in is sychronous with the write
         end                             // address.
endmodule

The behavioural model will be replaced with a RAM macrocell in the silicon implementation.

Each port of a RAM has an address input. The two essential rules for RAM inference are that

there is one expression that is clearly recognisable as the address for each port, and
the data read out is registered by the required number of pipeline broadside registers to match the latency of the target technology without any use (peeking) of the data in that pipeline.

Similar rules facilitate automated deployment of other structural resources (or FUs as we shall call them later). One example is the clock-enable flip flop (as per clock gating) and another is multiplier inference. The FPGA's DSP unit, which is essentially a pipelined multiplier, will be deployed where the tools can make sufficient structural matches