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Digital Logic Modelling

Illustratring the four-value logic level encoding for common gates.
In the four-value logic system each net (wire or signal), at a particular time, has one of the following logic values:

In this model, nets jump from one value to another in an instant. Real nets have a transit time.

The symbol `X' has a different meaning according to tool applied: it means `uncertain' during simulation and `dont-care' during logic synthesis.

The dont-care in logic synthesis enables logic minimisation (as done visually with Karnaugh maps).

Digital Logic Modelling

28: (C) 2008-18, DJ Greaves, University of Cambridge, Computer Laboratory.   TAPE MISSING ICON